TuxMonkey/bf_original_balance_chassis
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Merge branch 'develop'，rebase to next generation

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This commit is contained in:
NeoZng
2022-12-30 23:49:22 +08:00
parent a3631a5ca5 390e168b46
commit 08440ce116
5 changed files with 373 additions and 1 deletions
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93
basic_framework.ioc
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@@ -9,6 +9,9 @@ ADC1.master=1
CAD.formats=
CAD.pinconfig=
CAD.provider=
CAD.formats=
CAD.pinconfig=
CAD.provider=
CAN1.BS1=CAN_BS1_10TQ
CAN1.BS2=CAN_BS2_3TQ
CAN1.CalculateBaudRate=1000000
@@ -21,6 +24,19 @@ CAN2.CalculateBaudRate=1000000
CAN2.CalculateTimeQuantum=71.42857142857143
CAN2.IPParameters=CalculateTimeQuantum,BS1,BS2,Prescaler,CalculateBaudRate
CAN2.Prescaler=3
Dma.MEMTOMEM.5.Direction=DMA_MEMORY_TO_MEMORY
Dma.MEMTOMEM.5.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.MEMTOMEM.5.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.MEMTOMEM.5.Instance=DMA2_Stream3
Dma.MEMTOMEM.5.MemBurst=DMA_MBURST_SINGLE
Dma.MEMTOMEM.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.MEMTOMEM.5.MemInc=DMA_MINC_ENABLE
Dma.MEMTOMEM.5.Mode=DMA_NORMAL
Dma.MEMTOMEM.5.PeriphBurst=DMA_PBURST_SINGLE
Dma.MEMTOMEM.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.MEMTOMEM.5.PeriphInc=DMA_PINC_ENABLE
Dma.MEMTOMEM.5.Priority=DMA_PRIORITY_HIGH
Dma.MEMTOMEM.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.ADC1.12.Direction=DMA_PERIPH_TO_MEMORY
Dma.ADC1.12.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.ADC1.12.Instance=DMA2_Stream4
@@ -84,6 +100,11 @@ Dma.SPI1_RX.4.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI1_RX.4.Instance=DMA2_Stream0
Dma.SPI1_RX.4.MemBurst=DMA_MBURST_SINGLE
Dma.SPI1_RX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.Request5=MEMTOMEM
Dma.Request6=SPI1_RX
Dma.Request7=SPI1_TX
Dma.Request8=SPI2_RX
Dma.Request9=SPI2_TX
Dma.SPI1_RX.4.MemInc=DMA_MINC_ENABLE
Dma.SPI1_RX.4.Mode=DMA_NORMAL
Dma.SPI1_RX.4.PeriphBurst=DMA_PBURST_SINGLE
@@ -93,8 +114,60 @@ Dma.SPI1_RX.4.Priority=DMA_PRIORITY_LOW
Dma.SPI1_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.SPI1_TX.5.Direction=DMA_MEMORY_TO_PERIPH
Dma.SPI1_TX.5.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI1_TX.5.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI1_TX.5.FIFOThreshold=10
Dma.SPI1_RX.6.Direction=DMA_PERIPH_TO_MEMORY
Dma.SPI1_RX.6.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI1_RX.6.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI1_RX.6.Instance=DMA2_Stream0
Dma.SPI1_RX.6.MemBurst=DMA_MBURST_SINGLE
Dma.SPI1_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI1_RX.6.MemInc=DMA_MINC_ENABLE
Dma.SPI1_RX.6.Mode=DMA_NORMAL
Dma.SPI1_RX.6.PeriphBurst=DMA_PBURST_SINGLE
Dma.SPI1_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_RX.6.PeriphInc=DMA_PINC_DISABLE
Dma.SPI1_RX.6.Priority=DMA_PRIORITY_LOW
Dma.SPI1_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.SPI1_TX.7.Direction=DMA_MEMORY_TO_PERIPH
Dma.SPI1_TX.7.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI1_TX.7.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI1_TX.7.Instance=DMA2_StreamDMA_FIFO_THRESHOLD_FULL
Dma.SPI1_TX.5.Instance=DMA2_Stream3
Dma.SPI1_TX.7.MemBurst=DMA_MBURST_SINGLE
Dma.SPI1_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI1_TX.7.MemInc=DMA_MINC_ENABLE
Dma.SPI1_TX.7.Mode=DMA_NORMAL
Dma.SPI1_TX.7.PeriphBurst=DMA_PBURST_SINGLE
Dma.SPI1_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_TX.7.PeriphInc=DMA_PINC_DISABLE
Dma.SPI1_TX.7.Priority=DMA_PRIORITY_LOW
Dma.SPI1_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.SPI2_RX.8.Direction=DMA_PERIPH_TO_MEMORY
Dma.SPI2_RX.8.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI2_RX.8.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI2_RX.8.Instance=DMA1_Stream3
Dma.SPI2_RX.8.MemBurst=DMA_MBURST_SINGLE
Dma.SPI2_RX.8.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI2_RX.8.MemInc=DMA_MINC_ENABLE
Dma.SPI2_RX.8.Mode=DMA_NORMAL
Dma.SPI2_RX.8.PeriphBurst=DMA_PBURST_SINGLE
Dma.SPI2_RX.8.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI2_RX.8.PeriphInc=DMA_PINC_DISABLE
Dma.SPI2_RX.8.Priority=DMA_PRIORITY_LOW
Dma.SPI2_RX.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.SPI2_TX.9.Direction=DMA_MEMORY_TO_PERIPH
Dma.SPI2_TX.9.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI2_TX.9.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI2_TX.9.Instance=DMA1_Stream4
Dma.SPI2_TX.9.MemBurst=DMA_MBURST_SINGLE
Dma.SPI2_TX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI2_TX.9.MemInc=DMA_MINC_ENABLE
Dma.SPI2_TX.9.Mode=DMA_NORMAL
Dma.SPI2_TX.9.PeriphBurst=DMA_PBURST_SINGLE
Dma.SPI2_TX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI2_TX.9.PeriphInc=DMA_PINC_DISABLE
Dma.SPI2_TX.9.Priority=DMA_PRIORITY_LOW
Dma.SPI2_TX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.SPI1_TX.5.MemBurst=DMA_MBURST_SINGLE
Dma.SPI1_TX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI1_TX.5.MemInc=DMA_MINC_ENABLE
@@ -192,6 +265,10 @@ I2C2.I2C_Mode=I2C_Fast
I2C2.IPParameters=I2C_Mode
I2C3.I2C_Mode=I2C_Fast
I2C3.IPParameters=I2C_Mode
I2C2.I2C_Mode=I2C_Fast
I2C2.IPParameters=I2C_Mode
I2C3.I2C_Mode=I2C_Fast
I2C3.IPParameters=I2C_Mode
KeepUserPlacement=false
Mcu.CPN=STM32F407IGH6
Mcu.Family=STM32F4
@@ -236,6 +313,8 @@ Mcu.Pin16=PD1
Mcu.Pin17=PA11
Mcu.Pin18=PF0
Mcu.Pin19=PA9
Mcu.Pin18=PF0
Mcu.Pin19=PA9
Mcu.Pin2=PG14
Mcu.Pin20=PC9
Mcu.Pin21=PA8
@@ -247,6 +326,16 @@ Mcu.Pin26=PG6
Mcu.Pin27=PH12
Mcu.Pin28=PG3
Mcu.Pin29=PH11
Mcu.Pin20=PC9
Mcu.Pin21=PA8
Mcu.Pin22=PH0-OSC_IN
Mcu.Pin23=PH1-OSC_OUT
Mcu.Pin24=PF1
Mcu.Pin25=PC6
Mcu.Pin26=PG6
Mcu.Pin27=PH12
Mcu.Pin28=PG3
Mcu.Pin29=PH11
Mcu.Pin3=PB4
Mcu.Pin30=PH10
Mcu.Pin31=PD14
@@ -323,6 +412,8 @@ NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SPI1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.SPI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.SPI1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.SPI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
NVIC.SavedPendsvIrqHandlerGenerated=true
NVIC.SavedSvcallIrqHandlerGenerated=true