mirror of
https://gitee.com/dlmu-cone/bf_original_balance_chassis
synced 2026-07-23 19:25:09 +08:00
【务必拉取】修复ui发送使用临时变量buffer的问题,增加了DMAbuffer防止裁判系统接收溢出
This commit is contained in:
@@ -148,25 +148,31 @@ Dma.USART3_RX.7.PeriphInc=DMA_PINC_DISABLE
|
||||
Dma.USART3_RX.7.Priority=DMA_PRIORITY_LOW
|
||||
Dma.USART3_RX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
|
||||
Dma.USART6_RX.0.Direction=DMA_PERIPH_TO_MEMORY
|
||||
Dma.USART6_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
|
||||
Dma.USART6_RX.0.FIFOMode=DMA_FIFOMODE_ENABLE
|
||||
Dma.USART6_RX.0.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
|
||||
Dma.USART6_RX.0.Instance=DMA2_Stream2
|
||||
Dma.USART6_RX.0.MemBurst=DMA_MBURST_SINGLE
|
||||
Dma.USART6_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
|
||||
Dma.USART6_RX.0.MemInc=DMA_MINC_ENABLE
|
||||
Dma.USART6_RX.0.Mode=DMA_NORMAL
|
||||
Dma.USART6_RX.0.PeriphBurst=DMA_PBURST_SINGLE
|
||||
Dma.USART6_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
|
||||
Dma.USART6_RX.0.PeriphInc=DMA_PINC_DISABLE
|
||||
Dma.USART6_RX.0.Priority=DMA_PRIORITY_HIGH
|
||||
Dma.USART6_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
|
||||
Dma.USART6_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
|
||||
Dma.USART6_TX.1.Direction=DMA_MEMORY_TO_PERIPH
|
||||
Dma.USART6_TX.1.FIFOMode=DMA_FIFOMODE_DISABLE
|
||||
Dma.USART6_TX.1.FIFOMode=DMA_FIFOMODE_ENABLE
|
||||
Dma.USART6_TX.1.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
|
||||
Dma.USART6_TX.1.Instance=DMA2_Stream6
|
||||
Dma.USART6_TX.1.MemBurst=DMA_MBURST_SINGLE
|
||||
Dma.USART6_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
|
||||
Dma.USART6_TX.1.MemInc=DMA_MINC_ENABLE
|
||||
Dma.USART6_TX.1.Mode=DMA_NORMAL
|
||||
Dma.USART6_TX.1.PeriphBurst=DMA_PBURST_SINGLE
|
||||
Dma.USART6_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
|
||||
Dma.USART6_TX.1.PeriphInc=DMA_PINC_DISABLE
|
||||
Dma.USART6_TX.1.Priority=DMA_PRIORITY_HIGH
|
||||
Dma.USART6_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
|
||||
Dma.USART6_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
|
||||
FREERTOS.INCLUDE_vTaskDelayUntil=1
|
||||
FREERTOS.IPParameters=Tasks01,configENABLE_FPU,configMAX_TASK_NAME_LEN,configUSE_TIMERS,configUSE_POSIX_ERRNO,INCLUDE_vTaskDelayUntil
|
||||
FREERTOS.Tasks01=defaultTask,0,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL
|
||||
|
||||
Reference in New Issue
Block a user