mirror of
https://gitee.com/dlmu-cone/bf_original_balance_chassis
synced 2026-07-23 19:25:09 +08:00
增加了BSP PWM的支持,修改了bsp和module层的初始化提高可读性,新年快乐
This commit is contained in:
NeoZng
@@ -9,9 +9,6 @@ ADC1.master=1
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CAD.formats=
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CAD.pinconfig=
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CAD.provider=
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CAD.formats=
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CAD.pinconfig=
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CAD.provider=
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CAN1.BS1=CAN_BS1_10TQ
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CAN1.BS2=CAN_BS2_3TQ
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CAN1.CalculateBaudRate=1000000
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@@ -24,87 +21,55 @@ CAN2.CalculateBaudRate=1000000
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CAN2.CalculateTimeQuantum=71.42857142857143
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CAN2.IPParameters=CalculateTimeQuantum,BS1,BS2,Prescaler,CalculateBaudRate
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CAN2.Prescaler=3
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Dma.MEMTOMEM.5.Direction=DMA_MEMORY_TO_MEMORY
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Dma.MEMTOMEM.5.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.MEMTOMEM.5.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.MEMTOMEM.5.Instance=DMA2_Stream3
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Dma.MEMTOMEM.5.MemBurst=DMA_MBURST_SINGLE
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Dma.MEMTOMEM.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.MEMTOMEM.5.MemInc=DMA_MINC_ENABLE
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Dma.MEMTOMEM.5.Mode=DMA_NORMAL
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Dma.MEMTOMEM.5.PeriphBurst=DMA_PBURST_SINGLE
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Dma.MEMTOMEM.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.MEMTOMEM.5.PeriphInc=DMA_PINC_ENABLE
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Dma.MEMTOMEM.5.Priority=DMA_PRIORITY_HIGH
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Dma.MEMTOMEM.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.ADC1.12.Direction=DMA_PERIPH_TO_MEMORY
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Dma.ADC1.12.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.ADC1.12.Instance=DMA2_Stream4
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Dma.ADC1.12.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
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Dma.ADC1.12.MemInc=DMA_MINC_ENABLE
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Dma.ADC1.12.Mode=DMA_NORMAL
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Dma.ADC1.12.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
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Dma.ADC1.12.PeriphInc=DMA_PINC_DISABLE
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Dma.ADC1.12.Priority=DMA_PRIORITY_LOW
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Dma.ADC1.12.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.I2C2_RX.8.Direction=DMA_PERIPH_TO_MEMORY
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Dma.I2C2_RX.8.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.I2C2_RX.8.Instance=DMA1_Stream2
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Dma.I2C2_RX.8.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.I2C2_RX.8.MemInc=DMA_MINC_ENABLE
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Dma.I2C2_RX.8.Mode=DMA_NORMAL
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Dma.I2C2_RX.8.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.I2C2_RX.8.PeriphInc=DMA_PINC_DISABLE
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Dma.I2C2_RX.8.Priority=DMA_PRIORITY_LOW
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Dma.I2C2_RX.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.I2C2_TX.9.Direction=DMA_MEMORY_TO_PERIPH
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Dma.I2C2_TX.9.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.I2C2_TX.9.Instance=DMA1_Stream7
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Dma.I2C2_TX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.I2C2_TX.9.MemInc=DMA_MINC_ENABLE
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Dma.I2C2_TX.9.Mode=DMA_NORMAL
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Dma.I2C2_TX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.I2C2_TX.9.PeriphInc=DMA_PINC_DISABLE
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Dma.I2C2_TX.9.Priority=DMA_PRIORITY_LOW
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Dma.I2C2_TX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.MEMTOMEM.11.Direction=DMA_MEMORY_TO_MEMORY
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Dma.MEMTOMEM.11.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.MEMTOMEM.11.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.MEMTOMEM.11.Instance=DMA2_Stream5
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Dma.MEMTOMEM.11.MemBurst=DMA_MBURST_SINGLE
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Dma.MEMTOMEM.11.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.MEMTOMEM.11.MemInc=DMA_MINC_ENABLE
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Dma.MEMTOMEM.11.Mode=DMA_NORMAL
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Dma.MEMTOMEM.11.PeriphBurst=DMA_PBURST_SINGLE
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Dma.MEMTOMEM.11.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.MEMTOMEM.11.PeriphInc=DMA_PINC_ENABLE
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Dma.MEMTOMEM.11.Priority=DMA_PRIORITY_LOW
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Dma.MEMTOMEM.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.ADC1.8.Direction=DMA_PERIPH_TO_MEMORY
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Dma.ADC1.8.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.ADC1.8.Instance=DMA2_Stream4
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Dma.ADC1.8.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
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Dma.ADC1.8.MemInc=DMA_MINC_ENABLE
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Dma.ADC1.8.Mode=DMA_NORMAL
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Dma.ADC1.8.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
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Dma.ADC1.8.PeriphInc=DMA_PINC_DISABLE
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Dma.ADC1.8.Priority=DMA_PRIORITY_LOW
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Dma.ADC1.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.I2C2_RX.9.Direction=DMA_PERIPH_TO_MEMORY
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Dma.I2C2_RX.9.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.I2C2_RX.9.Instance=DMA1_Stream2
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Dma.I2C2_RX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.I2C2_RX.9.MemInc=DMA_MINC_ENABLE
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Dma.I2C2_RX.9.Mode=DMA_NORMAL
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Dma.I2C2_RX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.I2C2_RX.9.PeriphInc=DMA_PINC_DISABLE
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Dma.I2C2_RX.9.Priority=DMA_PRIORITY_LOW
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Dma.I2C2_RX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.I2C2_TX.10.Direction=DMA_MEMORY_TO_PERIPH
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Dma.I2C2_TX.10.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.I2C2_TX.10.Instance=DMA1_Stream7
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Dma.I2C2_TX.10.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.I2C2_TX.10.MemInc=DMA_MINC_ENABLE
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Dma.I2C2_TX.10.Mode=DMA_NORMAL
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Dma.I2C2_TX.10.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.I2C2_TX.10.PeriphInc=DMA_PINC_DISABLE
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Dma.I2C2_TX.10.Priority=DMA_PRIORITY_LOW
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Dma.I2C2_TX.10.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.Request0=USART6_RX
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Dma.Request1=USART6_TX
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Dma.Request10=USART3_RX
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Dma.Request11=MEMTOMEM
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Dma.Request12=ADC1
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Dma.Request10=I2C2_TX
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Dma.Request11=SPI1_TX
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Dma.Request2=USART1_TX
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Dma.Request3=USART1_RX
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Dma.Request4=SPI1_RX
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Dma.Request5=SPI1_TX
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Dma.Request6=SPI2_RX
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Dma.Request7=SPI2_TX
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Dma.Request8=I2C2_RX
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Dma.Request9=I2C2_TX
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Dma.RequestsNb=13
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Dma.Request5=SPI2_RX
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Dma.Request6=SPI2_TX
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Dma.Request7=USART3_RX
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Dma.Request8=ADC1
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Dma.Request9=I2C2_RX
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Dma.RequestsNb=12
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Dma.SPI1_RX.4.Direction=DMA_PERIPH_TO_MEMORY
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Dma.SPI1_RX.4.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI1_RX.4.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI1_RX.4.Instance=DMA2_Stream0
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Dma.SPI1_RX.4.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI1_RX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.Request5=MEMTOMEM
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Dma.Request6=SPI1_RX
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Dma.Request7=SPI1_TX
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Dma.Request8=SPI2_RX
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Dma.Request9=SPI2_TX
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Dma.SPI1_RX.4.MemInc=DMA_MINC_ENABLE
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Dma.SPI1_RX.4.Mode=DMA_NORMAL
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Dma.SPI1_RX.4.PeriphBurst=DMA_PBURST_SINGLE
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@@ -112,100 +77,45 @@ Dma.SPI1_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI1_RX.4.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI1_RX.4.Priority=DMA_PRIORITY_LOW
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Dma.SPI1_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI1_TX.5.Direction=DMA_MEMORY_TO_PERIPH
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Dma.SPI1_TX.5.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI1_TX.5.FIFOThreshold=10
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Dma.SPI1_RX.6.Direction=DMA_PERIPH_TO_MEMORY
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Dma.SPI1_RX.6.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI1_RX.6.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI1_RX.6.Instance=DMA2_Stream0
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Dma.SPI1_RX.6.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI1_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI1_RX.6.MemInc=DMA_MINC_ENABLE
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Dma.SPI1_RX.6.Mode=DMA_NORMAL
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Dma.SPI1_RX.6.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI1_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI1_RX.6.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI1_RX.6.Priority=DMA_PRIORITY_LOW
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Dma.SPI1_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI1_TX.7.Direction=DMA_MEMORY_TO_PERIPH
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Dma.SPI1_TX.7.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI1_TX.7.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI1_TX.7.Instance=DMA2_StreamDMA_FIFO_THRESHOLD_FULL
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Dma.SPI1_TX.5.Instance=DMA2_Stream3
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Dma.SPI1_TX.7.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI1_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI1_TX.7.MemInc=DMA_MINC_ENABLE
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Dma.SPI1_TX.7.Mode=DMA_NORMAL
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Dma.SPI1_TX.7.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI1_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI1_TX.7.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI1_TX.7.Priority=DMA_PRIORITY_LOW
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Dma.SPI1_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI2_RX.8.Direction=DMA_PERIPH_TO_MEMORY
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Dma.SPI2_RX.8.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI2_RX.8.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI2_RX.8.Instance=DMA1_Stream3
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Dma.SPI2_RX.8.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI2_RX.8.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI2_RX.8.MemInc=DMA_MINC_ENABLE
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Dma.SPI2_RX.8.Mode=DMA_NORMAL
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Dma.SPI2_RX.8.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI2_RX.8.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI2_RX.8.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI2_RX.8.Priority=DMA_PRIORITY_LOW
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Dma.SPI2_RX.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI2_TX.9.Direction=DMA_MEMORY_TO_PERIPH
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Dma.SPI2_TX.9.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI2_TX.9.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI2_TX.9.Instance=DMA1_Stream4
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Dma.SPI2_TX.9.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI2_TX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI2_TX.9.MemInc=DMA_MINC_ENABLE
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Dma.SPI2_TX.9.Mode=DMA_NORMAL
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Dma.SPI2_TX.9.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI2_TX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI2_TX.9.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI2_TX.9.Priority=DMA_PRIORITY_LOW
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Dma.SPI2_TX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI1_TX.5.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI1_TX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI1_TX.5.MemInc=DMA_MINC_ENABLE
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Dma.SPI1_TX.5.Mode=DMA_NORMAL
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Dma.SPI1_TX.5.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI1_TX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI1_TX.5.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI1_TX.5.Priority=DMA_PRIORITY_LOW
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Dma.SPI1_TX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI2_RX.6.Direction=DMA_PERIPH_TO_MEMORY
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Dma.SPI2_RX.6.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI2_RX.6.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI2_RX.6.Instance=DMA1_Stream3
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Dma.SPI2_RX.6.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI2_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI2_RX.6.MemInc=DMA_MINC_ENABLE
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Dma.SPI2_RX.6.Mode=DMA_NORMAL
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Dma.SPI2_RX.6.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI2_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI2_RX.6.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI2_RX.6.Priority=DMA_PRIORITY_LOW
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Dma.SPI2_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI2_TX.7.Direction=DMA_MEMORY_TO_PERIPH
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Dma.SPI2_TX.7.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI2_TX.7.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI2_TX.7.Instance=DMA1_Stream4
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Dma.SPI2_TX.7.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI2_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI2_TX.7.MemInc=DMA_MINC_ENABLE
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Dma.SPI2_TX.7.Mode=DMA_NORMAL
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Dma.SPI2_TX.7.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI2_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI2_TX.7.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI2_TX.7.Priority=DMA_PRIORITY_LOW
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Dma.SPI2_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI1_TX.11.Direction=DMA_MEMORY_TO_PERIPH
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Dma.SPI1_TX.11.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.SPI1_TX.11.Instance=DMA2_Stream3
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Dma.SPI1_TX.11.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI1_TX.11.MemInc=DMA_MINC_ENABLE
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Dma.SPI1_TX.11.Mode=DMA_NORMAL
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Dma.SPI1_TX.11.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI1_TX.11.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI1_TX.11.Priority=DMA_PRIORITY_LOW
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Dma.SPI1_TX.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.SPI2_RX.5.Direction=DMA_PERIPH_TO_MEMORY
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Dma.SPI2_RX.5.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI2_RX.5.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI2_RX.5.Instance=DMA1_Stream3
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Dma.SPI2_RX.5.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI2_RX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI2_RX.5.MemInc=DMA_MINC_ENABLE
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Dma.SPI2_RX.5.Mode=DMA_NORMAL
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Dma.SPI2_RX.5.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI2_RX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI2_RX.5.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI2_RX.5.Priority=DMA_PRIORITY_LOW
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Dma.SPI2_RX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI2_TX.6.Direction=DMA_MEMORY_TO_PERIPH
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Dma.SPI2_TX.6.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI2_TX.6.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI2_TX.6.Instance=DMA1_Stream4
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Dma.SPI2_TX.6.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI2_TX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI2_TX.6.MemInc=DMA_MINC_ENABLE
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Dma.SPI2_TX.6.Mode=DMA_NORMAL
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Dma.SPI2_TX.6.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI2_TX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI2_TX.6.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI2_TX.6.Priority=DMA_PRIORITY_LOW
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Dma.SPI2_TX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.USART1_RX.3.Direction=DMA_PERIPH_TO_MEMORY
|
||||
Dma.USART1_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE
|
||||
Dma.USART1_RX.3.Instance=DMA2_Stream2
|
||||
Dma.USART1_RX.3.Instance=DMA2_Stream5
|
||||
Dma.USART1_RX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE
|
||||
Dma.USART1_RX.3.MemInc=DMA_MINC_ENABLE
|
||||
Dma.USART1_RX.3.Mode=DMA_NORMAL
|
||||
@@ -223,19 +133,19 @@ Dma.USART1_TX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
|
||||
Dma.USART1_TX.2.PeriphInc=DMA_PINC_DISABLE
|
||||
Dma.USART1_TX.2.Priority=DMA_PRIORITY_VERY_HIGH
|
||||
Dma.USART1_TX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
|
||||
Dma.USART3_RX.10.Direction=DMA_PERIPH_TO_MEMORY
|
||||
Dma.USART3_RX.10.FIFOMode=DMA_FIFOMODE_DISABLE
|
||||
Dma.USART3_RX.10.Instance=DMA1_Stream1
|
||||
Dma.USART3_RX.10.MemDataAlignment=DMA_MDATAALIGN_BYTE
|
||||
Dma.USART3_RX.10.MemInc=DMA_MINC_ENABLE
|
||||
Dma.USART3_RX.10.Mode=DMA_NORMAL
|
||||
Dma.USART3_RX.10.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
|
||||
Dma.USART3_RX.10.PeriphInc=DMA_PINC_DISABLE
|
||||
Dma.USART3_RX.10.Priority=DMA_PRIORITY_LOW
|
||||
Dma.USART3_RX.10.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
|
||||
Dma.USART3_RX.7.Direction=DMA_PERIPH_TO_MEMORY
|
||||
Dma.USART3_RX.7.FIFOMode=DMA_FIFOMODE_DISABLE
|
||||
Dma.USART3_RX.7.Instance=DMA1_Stream1
|
||||
Dma.USART3_RX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
|
||||
Dma.USART3_RX.7.MemInc=DMA_MINC_ENABLE
|
||||
Dma.USART3_RX.7.Mode=DMA_NORMAL
|
||||
Dma.USART3_RX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
|
||||
Dma.USART3_RX.7.PeriphInc=DMA_PINC_DISABLE
|
||||
Dma.USART3_RX.7.Priority=DMA_PRIORITY_LOW
|
||||
Dma.USART3_RX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
|
||||
Dma.USART6_RX.0.Direction=DMA_PERIPH_TO_MEMORY
|
||||
Dma.USART6_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
|
||||
Dma.USART6_RX.0.Instance=DMA2_Stream1
|
||||
Dma.USART6_RX.0.Instance=DMA2_Stream2
|
||||
Dma.USART6_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
|
||||
Dma.USART6_RX.0.MemInc=DMA_MINC_ENABLE
|
||||
Dma.USART6_RX.0.Mode=DMA_NORMAL
|
||||
@@ -265,10 +175,6 @@ I2C2.I2C_Mode=I2C_Fast
|
||||
I2C2.IPParameters=I2C_Mode
|
||||
I2C3.I2C_Mode=I2C_Fast
|
||||
I2C3.IPParameters=I2C_Mode
|
||||
I2C2.I2C_Mode=I2C_Fast
|
||||
I2C2.IPParameters=I2C_Mode
|
||||
I2C3.I2C_Mode=I2C_Fast
|
||||
I2C3.IPParameters=I2C_Mode
|
||||
KeepUserPlacement=false
|
||||
Mcu.CPN=STM32F407IGH6
|
||||
Mcu.Family=STM32F4
|
||||
@@ -313,8 +219,6 @@ Mcu.Pin16=PD1
|
||||
Mcu.Pin17=PA11
|
||||
Mcu.Pin18=PF0
|
||||
Mcu.Pin19=PA9
|
||||
Mcu.Pin18=PF0
|
||||
Mcu.Pin19=PA9
|
||||
Mcu.Pin2=PG14
|
||||
Mcu.Pin20=PC9
|
||||
Mcu.Pin21=PA8
|
||||
@@ -326,16 +230,6 @@ Mcu.Pin26=PG6
|
||||
Mcu.Pin27=PH12
|
||||
Mcu.Pin28=PG3
|
||||
Mcu.Pin29=PH11
|
||||
Mcu.Pin20=PC9
|
||||
Mcu.Pin21=PA8
|
||||
Mcu.Pin22=PH0-OSC_IN
|
||||
Mcu.Pin23=PH1-OSC_OUT
|
||||
Mcu.Pin24=PF1
|
||||
Mcu.Pin25=PC6
|
||||
Mcu.Pin26=PG6
|
||||
Mcu.Pin27=PH12
|
||||
Mcu.Pin28=PG3
|
||||
Mcu.Pin29=PH11
|
||||
Mcu.Pin3=PB4
|
||||
Mcu.Pin30=PH10
|
||||
Mcu.Pin31=PD14
|
||||
@@ -391,11 +285,10 @@ NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA1_Stream7_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream1_IRQn=true\:5\:0\:false\:false\:true\:false\:false\:true\:true
|
||||
NVIC.DMA2_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:false\:false\:true\:true
|
||||
NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream5_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream5_IRQn=true\:5\:0\:false\:false\:true\:false\:false\:true\:true
|
||||
NVIC.DMA2_Stream6_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream7_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
@@ -412,8 +305,6 @@ NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false\:false
|
||||
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
|
||||
NVIC.SPI1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.SPI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.SPI1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.SPI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
|
||||
NVIC.SavedPendsvIrqHandlerGenerated=true
|
||||
NVIC.SavedSvcallIrqHandlerGenerated=true
|
||||
|
||||
Reference in New Issue
Block a user