mirror of
https://gitee.com/dlmu-cone/bf_original_balance_chassis
synced 2026-07-23 19:25:09 +08:00
重构bsp层，bsp层将和HAL的配置一致，修改CubeMX之后不需要修改bsp。重构bmi088。
This commit is contained in:
NeoZng
@@ -21,135 +21,171 @@ CAN2.CalculateBaudRate=1000000
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CAN2.CalculateTimeQuantum=71.42857142857143
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CAN2.IPParameters=CalculateTimeQuantum,BS1,BS2,Prescaler,CalculateBaudRate
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CAN2.Prescaler=3
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Dma.MEMTOMEM.5.Direction=DMA_MEMORY_TO_MEMORY
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Dma.MEMTOMEM.5.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.MEMTOMEM.5.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.MEMTOMEM.5.Instance=DMA2_Stream3
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Dma.MEMTOMEM.5.MemBurst=DMA_MBURST_SINGLE
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Dma.MEMTOMEM.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.MEMTOMEM.5.MemInc=DMA_MINC_ENABLE
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Dma.MEMTOMEM.5.Mode=DMA_NORMAL
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Dma.MEMTOMEM.5.PeriphBurst=DMA_PBURST_SINGLE
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Dma.MEMTOMEM.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.MEMTOMEM.5.PeriphInc=DMA_PINC_ENABLE
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Dma.MEMTOMEM.5.Priority=DMA_PRIORITY_HIGH
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Dma.MEMTOMEM.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.Request0=USART3_RX
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Dma.Request1=USART6_RX
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Dma.Request2=USART6_TX
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Dma.Request3=USART1_TX
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Dma.Request4=USART1_RX
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Dma.Request5=MEMTOMEM
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Dma.Request6=SPI1_RX
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Dma.Request7=SPI1_TX
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Dma.Request8=SPI2_RX
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Dma.Request9=SPI2_TX
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Dma.RequestsNb=10
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Dma.SPI1_RX.6.Direction=DMA_PERIPH_TO_MEMORY
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Dma.SPI1_RX.6.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI1_RX.6.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI1_RX.6.Instance=DMA2_Stream0
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Dma.SPI1_RX.6.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI1_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI1_RX.6.MemInc=DMA_MINC_ENABLE
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Dma.SPI1_RX.6.Mode=DMA_NORMAL
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Dma.SPI1_RX.6.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI1_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI1_RX.6.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI1_RX.6.Priority=DMA_PRIORITY_LOW
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Dma.SPI1_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI1_TX.7.Direction=DMA_MEMORY_TO_PERIPH
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Dma.SPI1_TX.7.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI1_TX.7.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI1_TX.7.Instance=DMA2_Stream5
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Dma.SPI1_TX.7.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI1_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI1_TX.7.MemInc=DMA_MINC_ENABLE
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Dma.SPI1_TX.7.Mode=DMA_NORMAL
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Dma.SPI1_TX.7.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI1_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI1_TX.7.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI1_TX.7.Priority=DMA_PRIORITY_LOW
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Dma.SPI1_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI2_RX.8.Direction=DMA_PERIPH_TO_MEMORY
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Dma.SPI2_RX.8.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI2_RX.8.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI2_RX.8.Instance=DMA1_Stream3
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Dma.SPI2_RX.8.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI2_RX.8.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI2_RX.8.MemInc=DMA_MINC_ENABLE
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Dma.SPI2_RX.8.Mode=DMA_NORMAL
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Dma.SPI2_RX.8.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI2_RX.8.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI2_RX.8.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI2_RX.8.Priority=DMA_PRIORITY_LOW
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Dma.SPI2_RX.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI2_TX.9.Direction=DMA_MEMORY_TO_PERIPH
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Dma.SPI2_TX.9.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI2_TX.9.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI2_TX.9.Instance=DMA1_Stream4
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Dma.SPI2_TX.9.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI2_TX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI2_TX.9.MemInc=DMA_MINC_ENABLE
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Dma.SPI2_TX.9.Mode=DMA_NORMAL
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Dma.SPI2_TX.9.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI2_TX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI2_TX.9.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI2_TX.9.Priority=DMA_PRIORITY_LOW
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Dma.SPI2_TX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.USART1_RX.4.Direction=DMA_PERIPH_TO_MEMORY
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Dma.USART1_RX.4.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.USART1_RX.4.Instance=DMA2_Stream2
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Dma.USART1_RX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.USART1_RX.4.MemInc=DMA_MINC_ENABLE
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Dma.USART1_RX.4.Mode=DMA_NORMAL
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Dma.USART1_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.USART1_RX.4.PeriphInc=DMA_PINC_DISABLE
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Dma.USART1_RX.4.Priority=DMA_PRIORITY_VERY_HIGH
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Dma.USART1_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.USART1_TX.3.Direction=DMA_MEMORY_TO_PERIPH
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Dma.USART1_TX.3.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.USART1_TX.3.Instance=DMA2_Stream7
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Dma.USART1_TX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.USART1_TX.3.MemInc=DMA_MINC_ENABLE
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Dma.USART1_TX.3.Mode=DMA_NORMAL
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Dma.USART1_TX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.USART1_TX.3.PeriphInc=DMA_PINC_DISABLE
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Dma.USART1_TX.3.Priority=DMA_PRIORITY_VERY_HIGH
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Dma.USART1_TX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.USART3_RX.0.Direction=DMA_PERIPH_TO_MEMORY
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Dma.USART3_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.USART3_RX.0.Instance=DMA1_Stream1
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Dma.USART3_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.USART3_RX.0.MemInc=DMA_MINC_ENABLE
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Dma.USART3_RX.0.Mode=DMA_NORMAL
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Dma.USART3_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.USART3_RX.0.PeriphInc=DMA_PINC_DISABLE
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Dma.USART3_RX.0.Priority=DMA_PRIORITY_VERY_HIGH
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Dma.USART3_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.USART6_RX.1.Direction=DMA_PERIPH_TO_MEMORY
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Dma.USART6_RX.1.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.USART6_RX.1.Instance=DMA2_Stream1
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Dma.USART6_RX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.USART6_RX.1.MemInc=DMA_MINC_ENABLE
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Dma.USART6_RX.1.Mode=DMA_NORMAL
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Dma.USART6_RX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.USART6_RX.1.PeriphInc=DMA_PINC_DISABLE
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Dma.USART6_RX.1.Priority=DMA_PRIORITY_HIGH
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Dma.USART6_RX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.USART6_TX.2.Direction=DMA_MEMORY_TO_PERIPH
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Dma.USART6_TX.2.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.USART6_TX.2.Instance=DMA2_Stream6
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Dma.USART6_TX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.USART6_TX.2.MemInc=DMA_MINC_ENABLE
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Dma.USART6_TX.2.Mode=DMA_NORMAL
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Dma.USART6_TX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.USART6_TX.2.PeriphInc=DMA_PINC_DISABLE
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Dma.USART6_TX.2.Priority=DMA_PRIORITY_HIGH
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Dma.USART6_TX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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FREERTOS.IPParameters=Tasks01,configENABLE_FPU
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Dma.ADC1.12.Direction=DMA_PERIPH_TO_MEMORY
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Dma.ADC1.12.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.ADC1.12.Instance=DMA2_Stream4
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Dma.ADC1.12.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
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Dma.ADC1.12.MemInc=DMA_MINC_ENABLE
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Dma.ADC1.12.Mode=DMA_NORMAL
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Dma.ADC1.12.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
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Dma.ADC1.12.PeriphInc=DMA_PINC_DISABLE
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Dma.ADC1.12.Priority=DMA_PRIORITY_LOW
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Dma.ADC1.12.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.I2C2_RX.8.Direction=DMA_PERIPH_TO_MEMORY
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Dma.I2C2_RX.8.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.I2C2_RX.8.Instance=DMA1_Stream2
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Dma.I2C2_RX.8.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.I2C2_RX.8.MemInc=DMA_MINC_ENABLE
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Dma.I2C2_RX.8.Mode=DMA_NORMAL
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Dma.I2C2_RX.8.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.I2C2_RX.8.PeriphInc=DMA_PINC_DISABLE
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Dma.I2C2_RX.8.Priority=DMA_PRIORITY_LOW
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Dma.I2C2_RX.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.I2C2_TX.9.Direction=DMA_MEMORY_TO_PERIPH
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Dma.I2C2_TX.9.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.I2C2_TX.9.Instance=DMA1_Stream7
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Dma.I2C2_TX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.I2C2_TX.9.MemInc=DMA_MINC_ENABLE
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Dma.I2C2_TX.9.Mode=DMA_NORMAL
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Dma.I2C2_TX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.I2C2_TX.9.PeriphInc=DMA_PINC_DISABLE
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Dma.I2C2_TX.9.Priority=DMA_PRIORITY_LOW
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Dma.I2C2_TX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.MEMTOMEM.11.Direction=DMA_MEMORY_TO_MEMORY
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Dma.MEMTOMEM.11.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.MEMTOMEM.11.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.MEMTOMEM.11.Instance=DMA2_Stream5
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Dma.MEMTOMEM.11.MemBurst=DMA_MBURST_SINGLE
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Dma.MEMTOMEM.11.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.MEMTOMEM.11.MemInc=DMA_MINC_ENABLE
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Dma.MEMTOMEM.11.Mode=DMA_NORMAL
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Dma.MEMTOMEM.11.PeriphBurst=DMA_PBURST_SINGLE
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Dma.MEMTOMEM.11.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.MEMTOMEM.11.PeriphInc=DMA_PINC_ENABLE
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Dma.MEMTOMEM.11.Priority=DMA_PRIORITY_LOW
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Dma.MEMTOMEM.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.Request0=USART6_RX
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Dma.Request1=USART6_TX
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Dma.Request10=USART3_RX
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Dma.Request11=MEMTOMEM
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Dma.Request12=ADC1
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Dma.Request2=USART1_TX
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Dma.Request3=USART1_RX
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Dma.Request4=SPI1_RX
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Dma.Request5=SPI1_TX
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Dma.Request6=SPI2_RX
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Dma.Request7=SPI2_TX
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Dma.Request8=I2C2_RX
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Dma.Request9=I2C2_TX
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Dma.RequestsNb=13
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Dma.SPI1_RX.4.Direction=DMA_PERIPH_TO_MEMORY
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Dma.SPI1_RX.4.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI1_RX.4.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI1_RX.4.Instance=DMA2_Stream0
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Dma.SPI1_RX.4.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI1_RX.4.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI1_RX.4.MemInc=DMA_MINC_ENABLE
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Dma.SPI1_RX.4.Mode=DMA_NORMAL
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Dma.SPI1_RX.4.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI1_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI1_RX.4.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI1_RX.4.Priority=DMA_PRIORITY_LOW
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Dma.SPI1_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI1_TX.5.Direction=DMA_MEMORY_TO_PERIPH
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Dma.SPI1_TX.5.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI1_TX.5.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI1_TX.5.Instance=DMA2_Stream3
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Dma.SPI1_TX.5.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI1_TX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI1_TX.5.MemInc=DMA_MINC_ENABLE
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Dma.SPI1_TX.5.Mode=DMA_NORMAL
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Dma.SPI1_TX.5.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI1_TX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI1_TX.5.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI1_TX.5.Priority=DMA_PRIORITY_LOW
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Dma.SPI1_TX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI2_RX.6.Direction=DMA_PERIPH_TO_MEMORY
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Dma.SPI2_RX.6.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI2_RX.6.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI2_RX.6.Instance=DMA1_Stream3
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Dma.SPI2_RX.6.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI2_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI2_RX.6.MemInc=DMA_MINC_ENABLE
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Dma.SPI2_RX.6.Mode=DMA_NORMAL
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Dma.SPI2_RX.6.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI2_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI2_RX.6.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI2_RX.6.Priority=DMA_PRIORITY_LOW
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Dma.SPI2_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.SPI2_TX.7.Direction=DMA_MEMORY_TO_PERIPH
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Dma.SPI2_TX.7.FIFOMode=DMA_FIFOMODE_ENABLE
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Dma.SPI2_TX.7.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
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Dma.SPI2_TX.7.Instance=DMA1_Stream4
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Dma.SPI2_TX.7.MemBurst=DMA_MBURST_SINGLE
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Dma.SPI2_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.SPI2_TX.7.MemInc=DMA_MINC_ENABLE
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Dma.SPI2_TX.7.Mode=DMA_NORMAL
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Dma.SPI2_TX.7.PeriphBurst=DMA_PBURST_SINGLE
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Dma.SPI2_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.SPI2_TX.7.PeriphInc=DMA_PINC_DISABLE
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Dma.SPI2_TX.7.Priority=DMA_PRIORITY_LOW
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Dma.SPI2_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
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Dma.USART1_RX.3.Direction=DMA_PERIPH_TO_MEMORY
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Dma.USART1_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.USART1_RX.3.Instance=DMA2_Stream2
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Dma.USART1_RX.3.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.USART1_RX.3.MemInc=DMA_MINC_ENABLE
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Dma.USART1_RX.3.Mode=DMA_NORMAL
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Dma.USART1_RX.3.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.USART1_RX.3.PeriphInc=DMA_PINC_DISABLE
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Dma.USART1_RX.3.Priority=DMA_PRIORITY_VERY_HIGH
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Dma.USART1_RX.3.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.USART1_TX.2.Direction=DMA_MEMORY_TO_PERIPH
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Dma.USART1_TX.2.FIFOMode=DMA_FIFOMODE_DISABLE
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Dma.USART1_TX.2.Instance=DMA2_Stream7
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Dma.USART1_TX.2.MemDataAlignment=DMA_MDATAALIGN_BYTE
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Dma.USART1_TX.2.MemInc=DMA_MINC_ENABLE
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Dma.USART1_TX.2.Mode=DMA_NORMAL
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Dma.USART1_TX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
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Dma.USART1_TX.2.PeriphInc=DMA_PINC_DISABLE
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Dma.USART1_TX.2.Priority=DMA_PRIORITY_VERY_HIGH
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Dma.USART1_TX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
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Dma.USART3_RX.10.Direction=DMA_PERIPH_TO_MEMORY
|
||||
Dma.USART3_RX.10.FIFOMode=DMA_FIFOMODE_DISABLE
|
||||
Dma.USART3_RX.10.Instance=DMA1_Stream1
|
||||
Dma.USART3_RX.10.MemDataAlignment=DMA_MDATAALIGN_BYTE
|
||||
Dma.USART3_RX.10.MemInc=DMA_MINC_ENABLE
|
||||
Dma.USART3_RX.10.Mode=DMA_NORMAL
|
||||
Dma.USART3_RX.10.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
|
||||
Dma.USART3_RX.10.PeriphInc=DMA_PINC_DISABLE
|
||||
Dma.USART3_RX.10.Priority=DMA_PRIORITY_LOW
|
||||
Dma.USART3_RX.10.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
|
||||
Dma.USART6_RX.0.Direction=DMA_PERIPH_TO_MEMORY
|
||||
Dma.USART6_RX.0.FIFOMode=DMA_FIFOMODE_DISABLE
|
||||
Dma.USART6_RX.0.Instance=DMA2_Stream1
|
||||
Dma.USART6_RX.0.MemDataAlignment=DMA_MDATAALIGN_BYTE
|
||||
Dma.USART6_RX.0.MemInc=DMA_MINC_ENABLE
|
||||
Dma.USART6_RX.0.Mode=DMA_NORMAL
|
||||
Dma.USART6_RX.0.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
|
||||
Dma.USART6_RX.0.PeriphInc=DMA_PINC_DISABLE
|
||||
Dma.USART6_RX.0.Priority=DMA_PRIORITY_HIGH
|
||||
Dma.USART6_RX.0.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
|
||||
Dma.USART6_TX.1.Direction=DMA_MEMORY_TO_PERIPH
|
||||
Dma.USART6_TX.1.FIFOMode=DMA_FIFOMODE_DISABLE
|
||||
Dma.USART6_TX.1.Instance=DMA2_Stream6
|
||||
Dma.USART6_TX.1.MemDataAlignment=DMA_MDATAALIGN_BYTE
|
||||
Dma.USART6_TX.1.MemInc=DMA_MINC_ENABLE
|
||||
Dma.USART6_TX.1.Mode=DMA_NORMAL
|
||||
Dma.USART6_TX.1.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
|
||||
Dma.USART6_TX.1.PeriphInc=DMA_PINC_DISABLE
|
||||
Dma.USART6_TX.1.Priority=DMA_PRIORITY_HIGH
|
||||
Dma.USART6_TX.1.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
|
||||
FREERTOS.IPParameters=Tasks01,configENABLE_FPU,configMAX_TASK_NAME_LEN,configUSE_TIMERS,configUSE_POSIX_ERRNO
|
||||
FREERTOS.Tasks01=defaultTask,0,128,StartDefaultTask,Default,NULL,Dynamic,NULL,NULL
|
||||
FREERTOS.configENABLE_FPU=1
|
||||
FREERTOS.configMAX_TASK_NAME_LEN=32
|
||||
FREERTOS.configUSE_POSIX_ERRNO=0
|
||||
FREERTOS.configUSE_TIMERS=0
|
||||
File.Version=6
|
||||
GPIO.groupedBy=Group By Peripherals
|
||||
I2C2.I2C_Mode=I2C_Fast
|
||||
@@ -161,29 +197,31 @@ Mcu.CPN=STM32F407IGH6
|
||||
Mcu.Family=STM32F4
|
||||
Mcu.IP0=ADC1
|
||||
Mcu.IP1=CAN1
|
||||
Mcu.IP10=RTC
|
||||
Mcu.IP11=SPI1
|
||||
Mcu.IP12=SPI2
|
||||
Mcu.IP13=SYS
|
||||
Mcu.IP14=TIM1
|
||||
Mcu.IP15=TIM4
|
||||
Mcu.IP16=TIM5
|
||||
Mcu.IP17=TIM8
|
||||
Mcu.IP18=TIM10
|
||||
Mcu.IP19=USART1
|
||||
Mcu.IP10=RCC
|
||||
Mcu.IP11=RNG
|
||||
Mcu.IP12=RTC
|
||||
Mcu.IP13=SPI1
|
||||
Mcu.IP14=SPI2
|
||||
Mcu.IP15=SYS
|
||||
Mcu.IP16=TIM1
|
||||
Mcu.IP17=TIM4
|
||||
Mcu.IP18=TIM5
|
||||
Mcu.IP19=TIM8
|
||||
Mcu.IP2=CAN2
|
||||
Mcu.IP20=USART3
|
||||
Mcu.IP21=USART6
|
||||
Mcu.IP22=USB_DEVICE
|
||||
Mcu.IP23=USB_OTG_FS
|
||||
Mcu.IP3=DMA
|
||||
Mcu.IP4=FREERTOS
|
||||
Mcu.IP5=I2C2
|
||||
Mcu.IP6=I2C3
|
||||
Mcu.IP7=NVIC
|
||||
Mcu.IP8=RCC
|
||||
Mcu.IP9=RNG
|
||||
Mcu.IPNb=24
|
||||
Mcu.IP20=TIM10
|
||||
Mcu.IP21=USART1
|
||||
Mcu.IP22=USART3
|
||||
Mcu.IP23=USART6
|
||||
Mcu.IP24=USB_DEVICE
|
||||
Mcu.IP25=USB_OTG_FS
|
||||
Mcu.IP3=CRC
|
||||
Mcu.IP4=DAC
|
||||
Mcu.IP5=DMA
|
||||
Mcu.IP6=FREERTOS
|
||||
Mcu.IP7=I2C2
|
||||
Mcu.IP8=I2C3
|
||||
Mcu.IP9=NVIC
|
||||
Mcu.IPNb=26
|
||||
Mcu.Name=STM32F407I(E-G)Hx
|
||||
Mcu.Package=UFBGA176
|
||||
Mcu.Pin0=PB8
|
||||
@@ -214,35 +252,39 @@ Mcu.Pin30=PH10
|
||||
Mcu.Pin31=PD14
|
||||
Mcu.Pin32=PA0-WKUP
|
||||
Mcu.Pin33=PA4
|
||||
Mcu.Pin34=PE13
|
||||
Mcu.Pin35=PE9
|
||||
Mcu.Pin36=PE11
|
||||
Mcu.Pin37=PE14
|
||||
Mcu.Pin38=PB13
|
||||
Mcu.Pin39=PA7
|
||||
Mcu.Pin34=PC4
|
||||
Mcu.Pin35=PE13
|
||||
Mcu.Pin36=PA5
|
||||
Mcu.Pin37=PC5
|
||||
Mcu.Pin38=PE9
|
||||
Mcu.Pin39=PE11
|
||||
Mcu.Pin4=PB3
|
||||
Mcu.Pin40=PB0
|
||||
Mcu.Pin41=PB14
|
||||
Mcu.Pin42=PB15
|
||||
Mcu.Pin43=VP_ADC1_TempSens_Input
|
||||
Mcu.Pin44=VP_ADC1_Vref_Input
|
||||
Mcu.Pin45=VP_FREERTOS_VS_CMSIS_V1
|
||||
Mcu.Pin46=VP_RNG_VS_RNG
|
||||
Mcu.Pin47=VP_RTC_VS_RTC_Activate
|
||||
Mcu.Pin48=VP_SYS_VS_Systick
|
||||
Mcu.Pin49=VP_TIM1_VS_ClockSourceINT
|
||||
Mcu.Pin40=PE14
|
||||
Mcu.Pin41=PB13
|
||||
Mcu.Pin42=PA7
|
||||
Mcu.Pin43=PB0
|
||||
Mcu.Pin44=PB14
|
||||
Mcu.Pin45=PB15
|
||||
Mcu.Pin46=VP_ADC1_TempSens_Input
|
||||
Mcu.Pin47=VP_ADC1_Vref_Input
|
||||
Mcu.Pin48=VP_CRC_VS_CRC
|
||||
Mcu.Pin49=VP_FREERTOS_VS_CMSIS_V1
|
||||
Mcu.Pin5=PA14
|
||||
Mcu.Pin50=VP_TIM4_VS_ClockSourceINT
|
||||
Mcu.Pin51=VP_TIM5_VS_ClockSourceINT
|
||||
Mcu.Pin52=VP_TIM8_VS_ClockSourceINT
|
||||
Mcu.Pin53=VP_TIM10_VS_ClockSourceINT
|
||||
Mcu.Pin54=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS
|
||||
Mcu.Pin55=VP_STMicroelectronics.X-CUBE-ALGOBUILD_VS_DSPOoLibraryJjLibrary_1.3.0_1.3.0
|
||||
Mcu.Pin50=VP_RNG_VS_RNG
|
||||
Mcu.Pin51=VP_RTC_VS_RTC_Activate
|
||||
Mcu.Pin52=VP_SYS_VS_Systick
|
||||
Mcu.Pin53=VP_TIM1_VS_ClockSourceINT
|
||||
Mcu.Pin54=VP_TIM4_VS_ClockSourceINT
|
||||
Mcu.Pin55=VP_TIM5_VS_ClockSourceINT
|
||||
Mcu.Pin56=VP_TIM8_VS_ClockSourceINT
|
||||
Mcu.Pin57=VP_TIM10_VS_ClockSourceINT
|
||||
Mcu.Pin58=VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS
|
||||
Mcu.Pin59=VP_STMicroelectronics.X-CUBE-ALGOBUILD_VS_DSPOoLibraryJjLibrary_1.3.0_1.3.0
|
||||
Mcu.Pin6=PA13
|
||||
Mcu.Pin7=PB7
|
||||
Mcu.Pin8=PB6
|
||||
Mcu.Pin9=PD0
|
||||
Mcu.PinsNb=56
|
||||
Mcu.PinsNb=60
|
||||
Mcu.ThirdParty0=STMicroelectronics.X-CUBE-ALGOBUILD.1.3.0
|
||||
Mcu.ThirdPartyNb=1
|
||||
Mcu.UserConstants=
|
||||
@@ -254,18 +296,26 @@ NVIC.CAN1_RX0_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true\:true
|
||||
NVIC.CAN1_RX1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.CAN2_RX0_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true\:true
|
||||
NVIC.CAN2_RX1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.DMA1_Stream1_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA1_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA1_Stream7_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream1_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream1_IRQn=true\:5\:0\:false\:false\:true\:false\:false\:true\:true
|
||||
NVIC.DMA2_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:false\:false\:true\:true
|
||||
NVIC.DMA2_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream5_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream6_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DMA2_Stream7_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
|
||||
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
NVIC.ForceEnableDMAVector=true
|
||||
NVIC.HardFault_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
NVIC.I2C2_ER_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.I2C2_EV_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.I2C3_ER_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.I2C3_EV_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
|
||||
NVIC.MemoryManagement_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
|
||||
NVIC.OTG_FS_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
|
||||
@@ -302,6 +352,7 @@ PA4.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
|
||||
PA4.Locked=true
|
||||
PA4.PinState=GPIO_PIN_SET
|
||||
PA4.Signal=GPIO_Output
|
||||
PA5.Signal=COMP_DAC2_group
|
||||
PA7.GPIOParameters=GPIO_PuPd
|
||||
PA7.GPIO_PuPd=GPIO_PULLUP
|
||||
PA7.Locked=true
|
||||
@@ -359,6 +410,16 @@ PC10.Signal=USART3_TX
|
||||
PC11.Locked=true
|
||||
PC11.Mode=Asynchronous
|
||||
PC11.Signal=USART3_RX
|
||||
PC4.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI
|
||||
PC4.GPIO_Label=INT_ACCEL
|
||||
PC4.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
|
||||
PC4.Locked=true
|
||||
PC4.Signal=GPXTI4
|
||||
PC5.GPIOParameters=GPIO_Label,GPIO_ModeDefaultEXTI
|
||||
PC5.GPIO_Label=INT_GYRO
|
||||
PC5.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
|
||||
PC5.Locked=true
|
||||
PC5.Signal=GPXTI5
|
||||
PC6.Locked=true
|
||||
PC6.Signal=S_TIM8_CH1
|
||||
PC9.Mode=I2C
|
||||
@@ -379,10 +440,8 @@ PE11.Signal=S_TIM1_CH2
|
||||
PE13.Locked=true
|
||||
PE13.Signal=S_TIM1_CH3
|
||||
PE14.Signal=S_TIM1_CH4
|
||||
PE9.GPIOParameters=GPIO_Speed,GPIO_PuPd,GPIO_Label
|
||||
PE9.GPIOParameters=GPIO_Label
|
||||
PE9.GPIO_Label=SERVO
|
||||
PE9.GPIO_PuPd=GPIO_PULLUP
|
||||
PE9.GPIO_Speed=GPIO_SPEED_FREQ_HIGH
|
||||
PE9.Locked=true
|
||||
PE9.Signal=S_TIM1_CH1
|
||||
PF0.Mode=I2C
|
||||
@@ -393,7 +452,7 @@ PG14.Locked=true
|
||||
PG14.Mode=Asynchronous
|
||||
PG14.Signal=USART6_TX
|
||||
PG3.GPIOParameters=GPIO_PuPd,GPIO_Label,GPIO_ModeDefaultEXTI
|
||||
PG3.GPIO_Label=MAG_DR
|
||||
PG3.GPIO_Label=INT_MAG
|
||||
PG3.GPIO_ModeDefaultEXTI=GPIO_MODE_IT_FALLING
|
||||
PG3.GPIO_PuPd=GPIO_PULLUP
|
||||
PG3.Locked=true
|
||||
@@ -460,7 +519,7 @@ ProjectManager.StackSize=0x4000
|
||||
ProjectManager.TargetToolchain=Makefile
|
||||
ProjectManager.ToolChainLocation=
|
||||
ProjectManager.UnderRoot=false
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_CAN1_Init-CAN1-false-HAL-true,6-MX_CAN2_Init-CAN2-false-HAL-true,7-MX_SPI1_Init-SPI1-false-HAL-true,8-MX_TIM4_Init-TIM4-false-HAL-true,9-MX_TIM5_Init-TIM5-false-HAL-true,10-MX_USART3_UART_Init-USART3-false-HAL-true,11-MX_RNG_Init-RNG-false-HAL-true,12-MX_RTC_Init-RTC-false-HAL-true,13-MX_TIM1_Init-TIM1-false-HAL-true,14-MX_TIM10_Init-TIM10-false-HAL-true,15-MX_USART1_UART_Init-USART1-false-HAL-true,16-MX_USART6_UART_Init-USART6-false-HAL-true,17-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false,18-MX_TIM8_Init-TIM8-false-HAL-true,19-MX_I2C2_Init-I2C2-false-HAL-true,20-MX_I2C3_Init-I2C3-false-HAL-true,21-MX_SPI2_Init-SPI2-false-HAL-true
|
||||
ProjectManager.functionlistsort=1-MX_GPIO_Init-GPIO-false-HAL-true,2-MX_DMA_Init-DMA-false-HAL-true,3-SystemClock_Config-RCC-false-HAL-false,4-MX_ADC1_Init-ADC1-false-HAL-true,5-MX_CAN1_Init-CAN1-false-HAL-true,6-MX_CAN2_Init-CAN2-false-HAL-true,7-MX_SPI1_Init-SPI1-false-HAL-true,8-MX_TIM4_Init-TIM4-false-HAL-true,9-MX_TIM5_Init-TIM5-false-HAL-true,10-MX_USART3_UART_Init-USART3-false-HAL-true,11-MX_RNG_Init-RNG-false-HAL-true,12-MX_RTC_Init-RTC-false-HAL-true,13-MX_TIM1_Init-TIM1-false-HAL-true,14-MX_TIM10_Init-TIM10-false-HAL-true,15-MX_USART1_UART_Init-USART1-false-HAL-true,16-MX_USART6_UART_Init-USART6-false-HAL-true,17-MX_USB_DEVICE_Init-USB_DEVICE-false-HAL-false,18-MX_TIM8_Init-TIM8-false-HAL-true,19-MX_I2C2_Init-I2C2-false-HAL-true,20-MX_I2C3_Init-I2C3-false-HAL-true,21-MX_SPI2_Init-SPI2-false-HAL-true,22-MX_CRC_Init-CRC-false-HAL-true,23-MX_DAC_Init-DAC-false-HAL-true
|
||||
RCC.48MHZClocksFreq_Value=48000000
|
||||
RCC.AHBFreq_Value=168000000
|
||||
RCC.APB1CLKDivider=RCC_HCLK_DIV4
|
||||
@@ -499,8 +558,14 @@ RCC.VcooutputI2S=192000000
|
||||
RTC.AsynchPrediv=124
|
||||
RTC.IPParameters=SynchPrediv,AsynchPrediv
|
||||
RTC.SynchPrediv=3199
|
||||
SH.COMP_DAC2_group.0=DAC_OUT2,DAC_OUT2
|
||||
SH.COMP_DAC2_group.ConfNb=1
|
||||
SH.GPXTI3.0=GPIO_EXTI3
|
||||
SH.GPXTI3.ConfNb=1
|
||||
SH.GPXTI4.0=GPIO_EXTI4
|
||||
SH.GPXTI4.ConfNb=1
|
||||
SH.GPXTI5.0=GPIO_EXTI5
|
||||
SH.GPXTI5.ConfNb=1
|
||||
SH.S_TIM10_CH1.0=TIM10_CH1,PWM Generation1 CH1
|
||||
SH.S_TIM10_CH1.ConfNb=1
|
||||
SH.S_TIM1_CH1.0=TIM1_CH1,PWM Generation1 CH1
|
||||
@@ -549,7 +614,7 @@ TIM1.Channel-PWM\ Generation1\ CH1=TIM_CHANNEL_1
|
||||
TIM1.Channel-PWM\ Generation2\ CH2=TIM_CHANNEL_2
|
||||
TIM1.Channel-PWM\ Generation3\ CH3=TIM_CHANNEL_3
|
||||
TIM1.Channel-PWM\ Generation4\ CH4=TIM_CHANNEL_4
|
||||
TIM1.IPParameters=Period,Prescaler,Channel-PWM Generation1 CH1,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4
|
||||
TIM1.IPParameters=Period,Prescaler,Channel-PWM Generation2 CH2,Channel-PWM Generation3 CH3,Channel-PWM Generation4 CH4,Channel-PWM Generation1 CH1
|
||||
TIM1.Period=19999
|
||||
TIM1.Prescaler=167
|
||||
TIM10.Channel=TIM_CHANNEL_1
|
||||
@@ -591,6 +656,8 @@ VP_ADC1_TempSens_Input.Mode=IN-TempSens
|
||||
VP_ADC1_TempSens_Input.Signal=ADC1_TempSens_Input
|
||||
VP_ADC1_Vref_Input.Mode=IN-Vrefint
|
||||
VP_ADC1_Vref_Input.Signal=ADC1_Vref_Input
|
||||
VP_CRC_VS_CRC.Mode=CRC_Activate
|
||||
VP_CRC_VS_CRC.Signal=CRC_VS_CRC
|
||||
VP_FREERTOS_VS_CMSIS_V1.Mode=CMSIS_V1
|
||||
VP_FREERTOS_VS_CMSIS_V1.Signal=FREERTOS_VS_CMSIS_V1
|
||||
VP_RNG_VS_RNG.Mode=RNG_Activate
|
||||
|
||||
Reference in New Issue
Block a user