TuxMonkey/bf_original_balance_chassis
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增加了spi的bsp支持

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This commit is contained in:
NeoZng
2022-12-28 23:12:25 +08:00
parent 25a0e24529
commit ab1a9726b1
10 changed files with 320 additions and 4 deletions
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78
basic_framework.ioc
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@@ -21,12 +21,82 @@ CAN2.CalculateBaudRate=1000000
CAN2.CalculateTimeQuantum=71.42857142857143
CAN2.IPParameters=CalculateTimeQuantum,BS1,BS2,Prescaler,CalculateBaudRate
CAN2.Prescaler=3
Dma.MEMTOMEM.5.Direction=DMA_MEMORY_TO_MEMORY
Dma.MEMTOMEM.5.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.MEMTOMEM.5.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.MEMTOMEM.5.Instance=DMA2_Stream3
Dma.MEMTOMEM.5.MemBurst=DMA_MBURST_SINGLE
Dma.MEMTOMEM.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.MEMTOMEM.5.MemInc=DMA_MINC_ENABLE
Dma.MEMTOMEM.5.Mode=DMA_NORMAL
Dma.MEMTOMEM.5.PeriphBurst=DMA_PBURST_SINGLE
Dma.MEMTOMEM.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.MEMTOMEM.5.PeriphInc=DMA_PINC_ENABLE
Dma.MEMTOMEM.5.Priority=DMA_PRIORITY_HIGH
Dma.MEMTOMEM.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.Request0=USART3_RX
Dma.Request1=USART6_RX
Dma.Request2=USART6_TX
Dma.Request3=USART1_TX
Dma.Request4=USART1_RX
Dma.RequestsNb=5
Dma.Request5=MEMTOMEM
Dma.Request6=SPI1_RX
Dma.Request7=SPI1_TX
Dma.Request8=SPI2_RX
Dma.Request9=SPI2_TX
Dma.RequestsNb=10
Dma.SPI1_RX.6.Direction=DMA_PERIPH_TO_MEMORY
Dma.SPI1_RX.6.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI1_RX.6.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI1_RX.6.Instance=DMA2_Stream0
Dma.SPI1_RX.6.MemBurst=DMA_MBURST_SINGLE
Dma.SPI1_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI1_RX.6.MemInc=DMA_MINC_ENABLE
Dma.SPI1_RX.6.Mode=DMA_NORMAL
Dma.SPI1_RX.6.PeriphBurst=DMA_PBURST_SINGLE
Dma.SPI1_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_RX.6.PeriphInc=DMA_PINC_DISABLE
Dma.SPI1_RX.6.Priority=DMA_PRIORITY_LOW
Dma.SPI1_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.SPI1_TX.7.Direction=DMA_MEMORY_TO_PERIPH
Dma.SPI1_TX.7.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI1_TX.7.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI1_TX.7.Instance=DMA2_Stream5
Dma.SPI1_TX.7.MemBurst=DMA_MBURST_SINGLE
Dma.SPI1_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI1_TX.7.MemInc=DMA_MINC_ENABLE
Dma.SPI1_TX.7.Mode=DMA_NORMAL
Dma.SPI1_TX.7.PeriphBurst=DMA_PBURST_SINGLE
Dma.SPI1_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_TX.7.PeriphInc=DMA_PINC_DISABLE
Dma.SPI1_TX.7.Priority=DMA_PRIORITY_LOW
Dma.SPI1_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.SPI2_RX.8.Direction=DMA_PERIPH_TO_MEMORY
Dma.SPI2_RX.8.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI2_RX.8.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI2_RX.8.Instance=DMA1_Stream3
Dma.SPI2_RX.8.MemBurst=DMA_MBURST_SINGLE
Dma.SPI2_RX.8.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI2_RX.8.MemInc=DMA_MINC_ENABLE
Dma.SPI2_RX.8.Mode=DMA_NORMAL
Dma.SPI2_RX.8.PeriphBurst=DMA_PBURST_SINGLE
Dma.SPI2_RX.8.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI2_RX.8.PeriphInc=DMA_PINC_DISABLE
Dma.SPI2_RX.8.Priority=DMA_PRIORITY_LOW
Dma.SPI2_RX.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.SPI2_TX.9.Direction=DMA_MEMORY_TO_PERIPH
Dma.SPI2_TX.9.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI2_TX.9.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI2_TX.9.Instance=DMA1_Stream4
Dma.SPI2_TX.9.MemBurst=DMA_MBURST_SINGLE
Dma.SPI2_TX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI2_TX.9.MemInc=DMA_MINC_ENABLE
Dma.SPI2_TX.9.Mode=DMA_NORMAL
Dma.SPI2_TX.9.PeriphBurst=DMA_PBURST_SINGLE
Dma.SPI2_TX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI2_TX.9.PeriphInc=DMA_PINC_DISABLE
Dma.SPI2_TX.9.Priority=DMA_PRIORITY_LOW
Dma.SPI2_TX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.USART1_RX.4.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART1_RX.4.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_RX.4.Instance=DMA2_Stream2
@@ -185,8 +255,12 @@ NVIC.CAN1_RX1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.CAN2_RX0_IRQn=true\:6\:0\:true\:false\:true\:true\:true\:true\:true
NVIC.CAN2_RX1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.DMA1_Stream1_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream1_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream5_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream6_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream7_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
@@ -197,6 +271,8 @@ NVIC.NonMaskableInt_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:fa
NVIC.OTG_FS_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.PendSV_IRQn=true\:15\:0\:false\:false\:false\:true\:false\:false\:false
NVIC.PriorityGroup=NVIC_PRIORITYGROUP_4
NVIC.SPI1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.SPI2_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.SVCall_IRQn=true\:0\:0\:false\:false\:false\:false\:false\:false\:false
NVIC.SavedPendsvIrqHandlerGenerated=true
NVIC.SavedSvcallIrqHandlerGenerated=true