TuxMonkey/bf_original_balance_chassis
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This commit is contained in:
chenfu
2023-12-09 14:52:17 +08:00
parent c2256da27c
commit b052126648
12 changed files with 157 additions and 289 deletions
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142
basic_framework.ioc
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@@ -25,49 +25,36 @@ CAN2.IPParameters=CalculateTimeQuantum,BS1,BS2,Prescaler,CalculateBaudRate,TXFP,
CAN2.NART=ENABLE
CAN2.Prescaler=3
CAN2.TXFP=ENABLE
Dma.ADC1.8.Direction=DMA_PERIPH_TO_MEMORY
Dma.ADC1.8.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.ADC1.8.Instance=DMA2_Stream4
Dma.ADC1.8.MemDataAlignment=DMA_MDATAALIGN_HALFWORD
Dma.ADC1.8.MemInc=DMA_MINC_ENABLE
Dma.ADC1.8.Mode=DMA_NORMAL
Dma.ADC1.8.PeriphDataAlignment=DMA_PDATAALIGN_HALFWORD
Dma.ADC1.8.PeriphInc=DMA_PINC_DISABLE
Dma.ADC1.8.Priority=DMA_PRIORITY_LOW
Dma.ADC1.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.I2C2_RX.9.Direction=DMA_PERIPH_TO_MEMORY
Dma.I2C2_RX.9.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.I2C2_RX.9.Instance=DMA1_Stream2
Dma.I2C2_RX.9.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.I2C2_RX.9.MemInc=DMA_MINC_ENABLE
Dma.I2C2_RX.9.Mode=DMA_NORMAL
Dma.I2C2_RX.9.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.I2C2_RX.9.PeriphInc=DMA_PINC_DISABLE
Dma.I2C2_RX.9.Priority=DMA_PRIORITY_LOW
Dma.I2C2_RX.9.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.I2C2_TX.10.Direction=DMA_MEMORY_TO_PERIPH
Dma.I2C2_TX.10.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.I2C2_TX.10.Instance=DMA1_Stream7
Dma.I2C2_TX.10.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.I2C2_TX.10.MemInc=DMA_MINC_ENABLE
Dma.I2C2_TX.10.Mode=DMA_NORMAL
Dma.I2C2_TX.10.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.I2C2_TX.10.PeriphInc=DMA_PINC_DISABLE
Dma.I2C2_TX.10.Priority=DMA_PRIORITY_LOW
Dma.I2C2_TX.10.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.I2C2_RX.6.Direction=DMA_PERIPH_TO_MEMORY
Dma.I2C2_RX.6.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.I2C2_RX.6.Instance=DMA1_Stream2
Dma.I2C2_RX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.I2C2_RX.6.MemInc=DMA_MINC_ENABLE
Dma.I2C2_RX.6.Mode=DMA_NORMAL
Dma.I2C2_RX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.I2C2_RX.6.PeriphInc=DMA_PINC_DISABLE
Dma.I2C2_RX.6.Priority=DMA_PRIORITY_LOW
Dma.I2C2_RX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.I2C2_TX.7.Direction=DMA_MEMORY_TO_PERIPH
Dma.I2C2_TX.7.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.I2C2_TX.7.Instance=DMA1_Stream7
Dma.I2C2_TX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.I2C2_TX.7.MemInc=DMA_MINC_ENABLE
Dma.I2C2_TX.7.Mode=DMA_NORMAL
Dma.I2C2_TX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.I2C2_TX.7.PeriphInc=DMA_PINC_DISABLE
Dma.I2C2_TX.7.Priority=DMA_PRIORITY_LOW
Dma.I2C2_TX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.Request0=USART6_RX
Dma.Request1=USART6_TX
Dma.Request10=I2C2_TX
Dma.Request11=SPI1_TX
Dma.Request2=USART1_TX
Dma.Request3=USART1_RX
Dma.Request4=SPI1_RX
Dma.Request5=SPI2_RX
Dma.Request6=SPI2_TX
Dma.Request7=USART3_RX
Dma.Request8=ADC1
Dma.Request9=I2C2_RX
Dma.RequestsNb=12
Dma.Request5=USART3_RX
Dma.Request6=I2C2_RX
Dma.Request7=I2C2_TX
Dma.Request8=SPI1_TX
Dma.RequestsNb=9
Dma.SPI1_RX.4.Direction=DMA_PERIPH_TO_MEMORY
Dma.SPI1_RX.4.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI1_RX.4.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
@@ -79,44 +66,18 @@ Dma.SPI1_RX.4.Mode=DMA_NORMAL
Dma.SPI1_RX.4.PeriphBurst=DMA_PBURST_SINGLE
Dma.SPI1_RX.4.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_RX.4.PeriphInc=DMA_PINC_DISABLE
Dma.SPI1_RX.4.Priority=DMA_PRIORITY_LOW
Dma.SPI1_RX.4.Priority=DMA_PRIORITY_HIGH
Dma.SPI1_RX.4.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.SPI1_TX.11.Direction=DMA_MEMORY_TO_PERIPH
Dma.SPI1_TX.11.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.SPI1_TX.11.Instance=DMA2_Stream3
Dma.SPI1_TX.11.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI1_TX.11.MemInc=DMA_MINC_ENABLE
Dma.SPI1_TX.11.Mode=DMA_NORMAL
Dma.SPI1_TX.11.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_TX.11.PeriphInc=DMA_PINC_DISABLE
Dma.SPI1_TX.11.Priority=DMA_PRIORITY_LOW
Dma.SPI1_TX.11.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.SPI2_RX.5.Direction=DMA_PERIPH_TO_MEMORY
Dma.SPI2_RX.5.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI2_RX.5.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI2_RX.5.Instance=DMA1_Stream3
Dma.SPI2_RX.5.MemBurst=DMA_MBURST_SINGLE
Dma.SPI2_RX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI2_RX.5.MemInc=DMA_MINC_ENABLE
Dma.SPI2_RX.5.Mode=DMA_NORMAL
Dma.SPI2_RX.5.PeriphBurst=DMA_PBURST_SINGLE
Dma.SPI2_RX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI2_RX.5.PeriphInc=DMA_PINC_DISABLE
Dma.SPI2_RX.5.Priority=DMA_PRIORITY_LOW
Dma.SPI2_RX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.SPI2_TX.6.Direction=DMA_MEMORY_TO_PERIPH
Dma.SPI2_TX.6.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.SPI2_TX.6.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
Dma.SPI2_TX.6.Instance=DMA1_Stream4
Dma.SPI2_TX.6.MemBurst=DMA_MBURST_SINGLE
Dma.SPI2_TX.6.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI2_TX.6.MemInc=DMA_MINC_ENABLE
Dma.SPI2_TX.6.Mode=DMA_NORMAL
Dma.SPI2_TX.6.PeriphBurst=DMA_PBURST_SINGLE
Dma.SPI2_TX.6.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI2_TX.6.PeriphInc=DMA_PINC_DISABLE
Dma.SPI2_TX.6.Priority=DMA_PRIORITY_LOW
Dma.SPI2_TX.6.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode,FIFOThreshold,MemBurst,PeriphBurst
Dma.SPI1_TX.8.Direction=DMA_MEMORY_TO_PERIPH
Dma.SPI1_TX.8.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.SPI1_TX.8.Instance=DMA2_Stream3
Dma.SPI1_TX.8.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.SPI1_TX.8.MemInc=DMA_MINC_ENABLE
Dma.SPI1_TX.8.Mode=DMA_NORMAL
Dma.SPI1_TX.8.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.SPI1_TX.8.PeriphInc=DMA_PINC_DISABLE
Dma.SPI1_TX.8.Priority=DMA_PRIORITY_HIGH
Dma.SPI1_TX.8.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.USART1_RX.3.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART1_RX.3.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART1_RX.3.Instance=DMA2_Stream5
@@ -137,16 +98,16 @@ Dma.USART1_TX.2.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART1_TX.2.PeriphInc=DMA_PINC_DISABLE
Dma.USART1_TX.2.Priority=DMA_PRIORITY_VERY_HIGH
Dma.USART1_TX.2.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.USART3_RX.7.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART3_RX.7.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART3_RX.7.Instance=DMA1_Stream1
Dma.USART3_RX.7.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_RX.7.MemInc=DMA_MINC_ENABLE
Dma.USART3_RX.7.Mode=DMA_NORMAL
Dma.USART3_RX.7.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_RX.7.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_RX.7.Priority=DMA_PRIORITY_LOW
Dma.USART3_RX.7.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.USART3_RX.5.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART3_RX.5.FIFOMode=DMA_FIFOMODE_DISABLE
Dma.USART3_RX.5.Instance=DMA1_Stream1
Dma.USART3_RX.5.MemDataAlignment=DMA_MDATAALIGN_BYTE
Dma.USART3_RX.5.MemInc=DMA_MINC_ENABLE
Dma.USART3_RX.5.Mode=DMA_NORMAL
Dma.USART3_RX.5.PeriphDataAlignment=DMA_PDATAALIGN_BYTE
Dma.USART3_RX.5.PeriphInc=DMA_PINC_DISABLE
Dma.USART3_RX.5.Priority=DMA_PRIORITY_LOW
Dma.USART3_RX.5.RequestParameters=Instance,Direction,PeriphInc,MemInc,PeriphDataAlignment,MemDataAlignment,Mode,Priority,FIFOMode
Dma.USART6_RX.0.Direction=DMA_PERIPH_TO_MEMORY
Dma.USART6_RX.0.FIFOMode=DMA_FIFOMODE_ENABLE
Dma.USART6_RX.0.FIFOThreshold=DMA_FIFO_THRESHOLD_FULL
@@ -295,14 +256,11 @@ NVIC.CAN2_RX0_IRQn=true\:5\:0\:true\:false\:true\:true\:true\:true\:true
NVIC.CAN2_RX1_IRQn=true\:5\:0\:false\:false\:true\:true\:true\:true\:true
NVIC.DMA1_Stream1_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA1_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA1_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA1_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA1_Stream7_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream0_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream0_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true
NVIC.DMA2_Stream2_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream3_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream4_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream5_IRQn=true\:5\:0\:false\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream3_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true
NVIC.DMA2_Stream5_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:true\:true
NVIC.DMA2_Stream6_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
NVIC.DMA2_Stream7_IRQn=true\:5\:0\:true\:false\:true\:true\:false\:true\:true
NVIC.DebugMonitor_IRQn=true\:0\:0\:false\:false\:true\:false\:false\:false\:false
@@ -518,6 +476,7 @@ ProjectManager.PreviousToolchain=
ProjectManager.ProjectBuild=false
ProjectManager.ProjectFileName=basic_framework.ioc
ProjectManager.ProjectName=basic_framework
ProjectManager.ProjectStructure=
ProjectManager.RegisterCallBack=
ProjectManager.StackSize=0x5000
ProjectManager.TargetToolchain=Makefile
@@ -689,3 +648,4 @@ VP_TIM8_VS_ClockSourceINT.Signal=TIM8_VS_ClockSourceINT
VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Mode=CDC_FS
VP_USB_DEVICE_VS_USB_DEVICE_CDC_FS.Signal=USB_DEVICE_VS_USB_DEVICE_CDC_FS
board=custom
rtos.0.ip=FREERTOS