mirror of
https://gitee.com/dlmu-cone/tronone-h7-scaffold
synced 2026-07-23 19:25:09 +08:00
ld file
This commit is contained in:
TuxMonkey
@@ -57,11 +57,11 @@
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#endif /* HSE_VALUE */
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#if !defined (CSI_VALUE)
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#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
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#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* CSI_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
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#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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@@ -142,17 +142,17 @@
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/** @addtogroup STM32H7xx_System_Private_Variables
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* @{
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*/
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 64000000;
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uint32_t SystemD2Clock = 64000000;
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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/* This variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 64000000;
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uint32_t SystemD2Clock = 64000000;
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const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
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/**
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* @}
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@@ -177,140 +177,149 @@
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* @param None
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* @retval None
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*/
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void SystemInit (void)
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void SystemInit(void)
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{
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#if defined (DATA_IN_D2_SRAM)
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__IO uint32_t tmpreg;
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__IO uint32_t tmpreg;
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#endif /* DATA_IN_D2_SRAM */
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Increasing the CPU frequency */
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if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
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{
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/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
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}
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/* Increasing the CPU frequency */
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if (FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
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{
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/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
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}
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/* Set HSION bit */
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RCC->CR |= RCC_CR_HSION;
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/* Set HSION bit */
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RCC->CR |= RCC_CR_HSION;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset CFGR register */
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RCC->CFGR = 0x00000000;
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/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
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RCC->CR &= 0xEAF6ED7FU;
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/* Reset HSEON, HSECSSON, CSION, HSI48ON, CSIKERON, PLL1ON, PLL2ON and PLL3ON bits */
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RCC->CR &= 0xEAF6ED7FU;
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/* Decreasing the number of wait states because of lower CPU frequency */
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if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
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{
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/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
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}
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/* Decreasing the number of wait states because of lower CPU frequency */
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if (FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
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{
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/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
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MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
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}
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#if defined(D3_SRAM_BASE)
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/* Reset D1CFGR register */
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RCC->D1CFGR = 0x00000000;
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/* Reset D1CFGR register */
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RCC->D1CFGR = 0x00000000;
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/* Reset D2CFGR register */
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RCC->D2CFGR = 0x00000000;
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/* Reset D2CFGR register */
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RCC->D2CFGR = 0x00000000;
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/* Reset D3CFGR register */
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RCC->D3CFGR = 0x00000000;
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/* Reset D3CFGR register */
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RCC->D3CFGR = 0x00000000;
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#else
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/* Reset CDCFGR1 register */
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RCC->CDCFGR1 = 0x00000000;
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/* Reset CDCFGR1 register */
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RCC->CDCFGR1 = 0x00000000;
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/* Reset CDCFGR2 register */
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RCC->CDCFGR2 = 0x00000000;
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/* Reset CDCFGR2 register */
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RCC->CDCFGR2 = 0x00000000;
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/* Reset SRDCFGR register */
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RCC->SRDCFGR = 0x00000000;
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/* Reset SRDCFGR register */
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RCC->SRDCFGR = 0x00000000;
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#endif
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/* Reset PLLCKSELR register */
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RCC->PLLCKSELR = 0x02020200;
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/* Reset PLLCKSELR register */
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RCC->PLLCKSELR = 0x02020200;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x01FF0000;
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/* Reset PLL1DIVR register */
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RCC->PLL1DIVR = 0x01010280;
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/* Reset PLL1FRACR register */
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RCC->PLL1FRACR = 0x00000000;
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/* Reset PLLCFGR register */
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RCC->PLLCFGR = 0x01FF0000;
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/* Reset PLL1DIVR register */
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RCC->PLL1DIVR = 0x01010280;
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/* Reset PLL1FRACR register */
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RCC->PLL1FRACR = 0x00000000;
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/* Reset PLL2DIVR register */
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RCC->PLL2DIVR = 0x01010280;
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/* Reset PLL2DIVR register */
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RCC->PLL2DIVR = 0x01010280;
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/* Reset PLL2FRACR register */
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/* Reset PLL2FRACR register */
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RCC->PLL2FRACR = 0x00000000;
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/* Reset PLL3DIVR register */
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RCC->PLL3DIVR = 0x01010280;
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RCC->PLL2FRACR = 0x00000000;
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/* Reset PLL3DIVR register */
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RCC->PLL3DIVR = 0x01010280;
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/* Reset PLL3FRACR register */
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RCC->PLL3FRACR = 0x00000000;
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/* Reset PLL3FRACR register */
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RCC->PLL3FRACR = 0x00000000;
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/* Reset HSEBYP bit */
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RCC->CR &= 0xFFFBFFFFU;
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/* Reset HSEBYP bit */
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RCC->CR &= 0xFFFBFFFFU;
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/* Disable all interrupts */
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RCC->CIER = 0x00000000;
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/* Disable all interrupts */
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RCC->CIER = 0x00000000;
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#if (STM32H7_DEV_ID == 0x450UL)
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/* dual core CM7 or single core line */
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if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
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{
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/* if stm32h7 revY*/
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/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
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*((__IO uint32_t*)0x51008108) = 0x000000001U;
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}
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/* dual core CM7 or single core line */
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if ((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
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{
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/* if stm32h7 revY*/
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/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
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*((__IO
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uint32_t *
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)
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0x51008108
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)
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=
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0x000000001U;
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}
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#endif /* STM32H7_DEV_ID */
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#if defined(DATA_IN_D2_SRAM)
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/* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
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/* in case of initialized data in D2 SRAM (AHB SRAM), enable the D2 SRAM clock (AHB SRAM clock) */
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#if defined(RCC_AHB2ENR_D2SRAM3EN)
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RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
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RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN | RCC_AHB2ENR_D2SRAM3EN);
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#elif defined(RCC_AHB2ENR_D2SRAM2EN)
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RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
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RCC->AHB2ENR |= (RCC_AHB2ENR_D2SRAM1EN | RCC_AHB2ENR_D2SRAM2EN);
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#else
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RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
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RCC->AHB2ENR |= (RCC_AHB2ENR_AHBSRAM1EN | RCC_AHB2ENR_AHBSRAM2EN);
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#endif /* RCC_AHB2ENR_D2SRAM3EN */
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tmpreg = RCC->AHB2ENR;
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(void) tmpreg;
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tmpreg = RCC->AHB2ENR;
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(void) tmpreg;
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#endif /* DATA_IN_D2_SRAM */
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#if defined(DUAL_CORE) && defined(CORE_CM4)
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/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
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/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
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#if defined(USER_VECT_TAB_ADDRESS)
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SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
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SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
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/* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
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#endif /* USER_VECT_TAB_ADDRESS */
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#else
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if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
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{
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/* Enable the FMC interface clock */
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SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
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if (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
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{
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/* Enable the FMC interface clock */
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SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
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/*
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* Disable the FMC bank1 (enabled after reset).
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* This, prevents CPU speculation access on this bank which blocks the use of FMC during
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* 24us. During this time the others FMC master (such as LTDC) cannot use it!
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*/
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FMC_Bank1_R->BTCR[0] = 0x000030D2;
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/*
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* Disable the FMC bank1 (enabled after reset).
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* This, prevents CPU speculation access on this bank which blocks the use of FMC during
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* 24us. During this time the others FMC master (such as LTDC) cannot use it!
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*/
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FMC_Bank1_R->BTCR[0] = 0x000030D2;
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/* Disable the FMC interface clock */
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CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
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}
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/* Disable the FMC interface clock */
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CLEAR_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
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}
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/* Configure the Vector Table location -------------------------------------*/
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/* Configure the Vector Table location -------------------------------------*/
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#if defined(USER_VECT_TAB_ADDRESS)
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SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
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SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
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/* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
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#endif /* USER_VECT_TAB_ADDRESS */
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__HAL_RCC_D2SRAM1_CLK_ENABLE(); //添加如下代码使能D2域的RAM（之用的ram_1,顺便把ram_d2也使能了）
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__HAL_RCC_D2SRAM2_CLK_ENABLE(); //ps.不使能的话会导致变量显式初始化无法赋值
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#endif /*DUAL_CORE && CORE_CM4*/
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}
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@@ -351,102 +360,112 @@ void SystemInit (void)
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate (void)
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void SystemCoreClockUpdate(void)
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{
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uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
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uint32_t common_system_clock;
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float_t fracn1, pllvco;
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uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
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uint32_t common_system_clock;
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float_t fracn1, pllvco;
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/* Get SYSCLK source -------------------------------------------------------*/
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR & RCC_CFGR_SWS)
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{
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case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
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common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
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break;
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case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
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common_system_clock = CSI_VALUE;
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break;
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case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
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common_system_clock = HSE_VALUE;
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break;
|
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|
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case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
|
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
|
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SYSCLK = PLL_VCO / PLLR
|
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*/
|
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pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
|
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pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ;
|
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pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos);
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fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3));
|
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|
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if (pllm != 0U)
|
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switch (RCC->CFGR & RCC_CFGR_SWS)
|
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{
|
||||
switch (pllsource)
|
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{
|
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case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
|
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case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
|
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common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
|
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break;
|
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|
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hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
|
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pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
|
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common_system_clock = CSI_VALUE;
|
||||
break;
|
||||
|
||||
break;
|
||||
case RCC_CFGR_SWS_HSE: /* HSE used as system clock source */
|
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common_system_clock = HSE_VALUE;
|
||||
break;
|
||||
|
||||
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
|
||||
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
case RCC_CFGR_SWS_PLL1: /* PLL1 used as system clock source */
|
||||
|
||||
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
|
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pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
/* PLL_VCO = (HSE_VALUE or HSI_VALUE or CSI_VALUE/ PLLM) * PLLN
|
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SYSCLK = PLL_VCO / PLLR
|
||||
*/
|
||||
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
|
||||
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
|
||||
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
|
||||
fracn1 = (float_t) (uint32_t) (pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
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||||
|
||||
default:
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ;
|
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pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 );
|
||||
break;
|
||||
}
|
||||
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ;
|
||||
common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp);
|
||||
if (pllm != 0U)
|
||||
{
|
||||
switch (pllsource)
|
||||
{
|
||||
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
|
||||
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
|
||||
pllvco = ((float_t) hsivalue / (float_t) pllm) * (
|
||||
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
|
||||
fracn1 / (float_t) 0x2000) + (float_t) 1);
|
||||
|
||||
break;
|
||||
|
||||
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
|
||||
pllvco = ((float_t) CSI_VALUE / (float_t) pllm) * (
|
||||
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
|
||||
fracn1 / (float_t) 0x2000) + (float_t) 1);
|
||||
break;
|
||||
|
||||
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
|
||||
pllvco = ((float_t) HSE_VALUE / (float_t) pllm) * (
|
||||
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
|
||||
fracn1 / (float_t) 0x2000) + (float_t) 1);
|
||||
break;
|
||||
|
||||
default:
|
||||
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
|
||||
pllvco = ((float_t) hsivalue / (float_t) pllm) * (
|
||||
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
|
||||
fracn1 / (float_t) 0x2000) + (float_t) 1);
|
||||
break;
|
||||
}
|
||||
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U);
|
||||
common_system_clock = (uint32_t) (float_t) (pllvco / (float_t) pllp);
|
||||
}
|
||||
else
|
||||
{
|
||||
common_system_clock = 0U;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
|
||||
break;
|
||||
}
|
||||
else
|
||||
{
|
||||
common_system_clock = 0U;
|
||||
}
|
||||
break;
|
||||
|
||||
default:
|
||||
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3));
|
||||
break;
|
||||
}
|
||||
|
||||
/* Compute SystemClock frequency --------------------------------------------------*/
|
||||
/* Compute SystemClock frequency --------------------------------------------------*/
|
||||
#if defined (RCC_D1CFGR_D1CPRE)
|
||||
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos];
|
||||
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos];
|
||||
|
||||
/* common_system_clock frequency : CM7 CPU frequency */
|
||||
common_system_clock >>= tmp;
|
||||
/* common_system_clock frequency : CM7 CPU frequency */
|
||||
common_system_clock >>= tmp;
|
||||
|
||||
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
|
||||
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU));
|
||||
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
|
||||
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos])
|
||||
& 0x1FU));
|
||||
|
||||
#else
|
||||
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos];
|
||||
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos];
|
||||
|
||||
/* common_system_clock frequency : CM7 CPU frequency */
|
||||
common_system_clock >>= tmp;
|
||||
/* common_system_clock frequency : CM7 CPU frequency */
|
||||
common_system_clock >>= tmp;
|
||||
|
||||
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
|
||||
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
|
||||
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */
|
||||
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[
|
||||
(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(DUAL_CORE) && defined(CORE_CM4)
|
||||
SystemCoreClock = SystemD2Clock;
|
||||
SystemCoreClock = SystemD2Clock;
|
||||
#else
|
||||
SystemCoreClock = common_system_clock;
|
||||
SystemCoreClock = common_system_clock;
|
||||
#endif /* DUAL_CORE && CORE_CM4 */
|
||||
}
|
||||
|
||||
@@ -476,70 +495,81 @@ void SystemCoreClockUpdate (void)
|
||||
void ExitRun0Mode(void)
|
||||
{
|
||||
#if defined(USE_PWR_LDO_SUPPLY)
|
||||
#if defined(SMPS)
|
||||
#if defined(SMPS)
|
||||
/* Exit Run* mode by disabling SMPS and enabling LDO */
|
||||
PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN;
|
||||
#else
|
||||
#else
|
||||
/* Enable LDO mode */
|
||||
PWR->CR3 |= PWR_CR3_LDOEN;
|
||||
#endif /* SMPS */
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{}
|
||||
#endif /* SMPS */
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{
|
||||
}
|
||||
#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY)
|
||||
#if defined(SMPS)
|
||||
#if defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
|
||||
#else
|
||||
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
|
||||
#endif /* SMPS */
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{}
|
||||
#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 &= ~(PWR_CR3_LDOEN);
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{}
|
||||
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{}
|
||||
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{}
|
||||
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{}
|
||||
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{}
|
||||
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{}
|
||||
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{}
|
||||
#else
|
||||
/* No system power supply configuration is selected at exit Run* mode */
|
||||
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
|
||||
#endif /* SMPS */
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{
|
||||
}
|
||||
#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 &= ~(PWR_CR3_LDOEN);
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{
|
||||
}
|
||||
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{
|
||||
}
|
||||
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{
|
||||
}
|
||||
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{
|
||||
}
|
||||
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{
|
||||
}
|
||||
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN |
|
||||
PWR_CR3_BYPASS;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{
|
||||
}
|
||||
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS)
|
||||
/* Exit Run* mode */
|
||||
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN |
|
||||
PWR_CR3_BYPASS;
|
||||
/* Wait till voltage level flag is set */
|
||||
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
|
||||
{
|
||||
}
|
||||
#else
|
||||
/* No system power supply configuration is selected at exit Run* mode */
|
||||
#endif /* USE_PWR_LDO_SUPPLY */
|
||||
}
|
||||
|
||||
|
||||
Reference in New Issue
Block a user