TuxMonkey/tronone-h7-scaffold
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TuxMonkey
2025-11-20 15:33:09 +08:00
parent 922370eeec
commit a46ac6e1d8
1 changed files with 259 additions and 229 deletions
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72
Core/Src/system_stm32h7xx.c
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@@ -265,7 +265,13 @@ void SystemInit (void)
{ {
/* if stm32h7 revY*/ /* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U; *((__IO
uint32_t *
)
0x51008108
)
=
0x000000001U;
} }
#endif /* STM32H7_DEV_ID */ #endif /* STM32H7_DEV_ID */
@@ -286,7 +292,8 @@ void SystemInit (void)
#if defined(DUAL_CORE) && defined(CORE_CM4) #if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
#if defined(USER_VECT_TAB_ADDRESS) #if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
/* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */ #endif /* USER_VECT_TAB_ADDRESS */
#else #else
@@ -308,9 +315,11 @@ void SystemInit (void)
/* Configure the Vector Table location -------------------------------------*/ /* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS) #if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
/* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */ #endif /* USER_VECT_TAB_ADDRESS */
__HAL_RCC_D2SRAM1_CLK_ENABLE(); //添加如下代码使能D2域的RAM（之用的ram_1,顺便把ram_d2也使能了）
__HAL_RCC_D2SRAM2_CLK_ENABLE(); //ps.不使能的话会导致变量显式初始化无法赋值
#endif /*DUAL_CORE && CORE_CM4*/ #endif /*DUAL_CORE && CORE_CM4*/
} }
@@ -391,21 +400,29 @@ void SystemCoreClockUpdate (void)
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)); hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); pllvco = ((float_t) hsivalue / (float_t) pllm) * (
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
fracn1 / (float_t) 0x2000) + (float_t) 1);
break; break;
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); pllvco = ((float_t) CSI_VALUE / (float_t) pllm) * (
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
fracn1 / (float_t) 0x2000) + (float_t) 1);
break; break;
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); pllvco = ((float_t) HSE_VALUE / (float_t) pllm) * (
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
fracn1 / (float_t) 0x2000) + (float_t) 1);
break; break;
default: default:
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3)); hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); pllvco = ((float_t) hsivalue / (float_t) pllm) * (
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
fracn1 / (float_t) 0x2000) + (float_t) 1);
break; break;
} }
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U); pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U);
@@ -430,7 +447,8 @@ void SystemCoreClockUpdate (void)
common_system_clock >>= tmp; common_system_clock >>= tmp;
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos])
& 0x1FU));
#else #else
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]; tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos];
@@ -439,7 +457,8 @@ void SystemCoreClockUpdate (void)
common_system_clock >>= tmp; common_system_clock >>= tmp;
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */ /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[
(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif #endif
@@ -485,7 +504,8 @@ void ExitRun0Mode(void)
#endif /* SMPS */ #endif /* SMPS */
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) #elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY)
#if defined(SMPS) #if defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
@@ -495,49 +515,59 @@ void ExitRun0Mode(void)
#endif /* SMPS */ #endif /* SMPS */
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) #elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 &= ~(PWR_CR3_LDOEN); PWR->CR3 &= ~(PWR_CR3_LDOEN);
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN |
PWR_CR3_BYPASS;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN |
PWR_CR3_BYPASS;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#else #else
/* No system power supply configuration is selected at exit Run* mode */ /* No system power supply configuration is selected at exit Run* mode */
#endif /* USE_PWR_LDO_SUPPLY */ #endif /* USE_PWR_LDO_SUPPLY */