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TuxMonkey
2025-11-20 15:33:09 +08:00
parent 922370eeec
commit a46ac6e1d8
1 changed files with 259 additions and 229 deletions
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138
Core/Src/system_stm32h7xx.c
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@@ -57,11 +57,11 @@
#endif /* HSE_VALUE */ #endif /* HSE_VALUE */
#if !defined (CSI_VALUE) #if !defined (CSI_VALUE)
#define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/ #define CSI_VALUE ((uint32_t)4000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* CSI_VALUE */ #endif /* CSI_VALUE */
#if !defined (HSI_VALUE) #if !defined (HSI_VALUE)
#define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/ #define HSI_VALUE ((uint32_t)64000000) /*!< Value of the Internal oscillator in Hz*/
#endif /* HSI_VALUE */ #endif /* HSI_VALUE */
@@ -142,17 +142,17 @@
/** @addtogroup STM32H7xx_System_Private_Variables /** @addtogroup STM32H7xx_System_Private_Variables
* @{ * @{
*/ */
/* This variable is updated in three ways: /* This variable is updated in three ways:
1) by calling CMSIS function SystemCoreClockUpdate() 1) by calling CMSIS function SystemCoreClockUpdate()
2) by calling HAL API function HAL_RCC_GetHCLKFreq() 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
Note: If you use this function to configure the system clock; then there Note: If you use this function to configure the system clock; then there
is no need to call the 2 first functions listed above, since SystemCoreClock is no need to call the 2 first functions listed above, since SystemCoreClock
variable is updated automatically. variable is updated automatically.
*/ */
uint32_t SystemCoreClock = 64000000; uint32_t SystemCoreClock = 64000000;
uint32_t SystemD2Clock = 64000000; uint32_t SystemD2Clock = 64000000;
const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; const uint8_t D1CorePrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
/** /**
* @} * @}
@@ -177,20 +177,20 @@
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemInit (void) void SystemInit(void)
{ {
#if defined (DATA_IN_D2_SRAM) #if defined (DATA_IN_D2_SRAM)
__IO uint32_t tmpreg; __IO uint32_t tmpreg;
#endif /* DATA_IN_D2_SRAM */ #endif /* DATA_IN_D2_SRAM */
/* FPU settings ------------------------------------------------------------*/ /* FPU settings ------------------------------------------------------------*/
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
SCB->CPACR |= ((3UL << (10*2))|(3UL << (11*2))); /* set CP10 and CP11 Full Access */ SCB->CPACR |= ((3UL << (10 * 2)) | (3UL << (11 * 2))); /* set CP10 and CP11 Full Access */
#endif #endif
/* Reset the RCC clock configuration to the default reset state ------------*/ /* Reset the RCC clock configuration to the default reset state ------------*/
/* Increasing the CPU frequency */ /* Increasing the CPU frequency */
if(FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) if (FLASH_LATENCY_DEFAULT > (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{ {
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
@@ -206,7 +206,7 @@ void SystemInit (void)
RCC->CR &= 0xEAF6ED7FU; RCC->CR &= 0xEAF6ED7FU;
/* Decreasing the number of wait states because of lower CPU frequency */ /* Decreasing the number of wait states because of lower CPU frequency */
if(FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))) if (FLASH_LATENCY_DEFAULT < (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY)))
{ {
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */ /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT)); MODIFY_REG(FLASH->ACR, FLASH_ACR_LATENCY, (uint32_t)(FLASH_LATENCY_DEFAULT));
@@ -261,11 +261,17 @@ void SystemInit (void)
#if (STM32H7_DEV_ID == 0x450UL) #if (STM32H7_DEV_ID == 0x450UL)
/* dual core CM7 or single core line */ /* dual core CM7 or single core line */
if((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U) if ((DBGMCU->IDCODE & 0xFFFF0000U) < 0x20000000U)
{ {
/* if stm32h7 revY*/ /* if stm32h7 revY*/
/* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */ /* Change the switch matrix read issuing capability to 1 for the AXI SRAM target (Target 7) */
*((__IO uint32_t*)0x51008108) = 0x000000001U; *((__IO
uint32_t *
)
0x51008108
)
=
0x000000001U;
} }
#endif /* STM32H7_DEV_ID */ #endif /* STM32H7_DEV_ID */
@@ -286,11 +292,12 @@ void SystemInit (void)
#if defined(DUAL_CORE) && defined(CORE_CM4) #if defined(DUAL_CORE) && defined(CORE_CM4)
/* Configure the Vector Table location add offset address for cortex-M4 ------------------*/ /* Configure the Vector Table location add offset address for cortex-M4 ------------------*/
#if defined(USER_VECT_TAB_ADDRESS) #if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
/* Vector Table Relocation in Internal D2 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */ #endif /* USER_VECT_TAB_ADDRESS */
#else #else
if(READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U) if (READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN) == 0U)
{ {
/* Enable the FMC interface clock */ /* Enable the FMC interface clock */
SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN); SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);
@@ -308,9 +315,11 @@ void SystemInit (void)
/* Configure the Vector Table location -------------------------------------*/ /* Configure the Vector Table location -------------------------------------*/
#if defined(USER_VECT_TAB_ADDRESS) #if defined(USER_VECT_TAB_ADDRESS)
SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */ SCB->VTOR = VECT_TAB_BASE_ADDRESS | VECT_TAB_OFFSET;
/* Vector Table Relocation in Internal D1 AXI-RAM or in Internal FLASH */
#endif /* USER_VECT_TAB_ADDRESS */ #endif /* USER_VECT_TAB_ADDRESS */
__HAL_RCC_D2SRAM1_CLK_ENABLE(); //添加如下代码使能D2域的RAM（之用的ram_1,顺便把ram_d2也使能了）
__HAL_RCC_D2SRAM2_CLK_ENABLE(); //ps.不使能的话会导致变量显式初始化无法赋值
#endif /*DUAL_CORE && CORE_CM4*/ #endif /*DUAL_CORE && CORE_CM4*/
} }
@@ -351,7 +360,7 @@ void SystemInit (void)
* @param None * @param None
* @retval None * @retval None
*/ */
void SystemCoreClockUpdate (void) void SystemCoreClockUpdate(void)
{ {
uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp; uint32_t pllp, pllsource, pllm, pllfracen, hsivalue, tmp;
uint32_t common_system_clock; uint32_t common_system_clock;
@@ -363,7 +372,7 @@ void SystemCoreClockUpdate (void)
switch (RCC->CFGR & RCC_CFGR_SWS) switch (RCC->CFGR & RCC_CFGR_SWS)
{ {
case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */ case RCC_CFGR_SWS_HSI: /* HSI used as system clock source */
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
break; break;
case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */ case RCC_CFGR_SWS_CSI: /* CSI used as system clock source */
@@ -380,9 +389,9 @@ void SystemCoreClockUpdate (void)
SYSCLK = PLL_VCO / PLLR SYSCLK = PLL_VCO / PLLR
*/ */
pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC); pllsource = (RCC->PLLCKSELR & RCC_PLLCKSELR_PLLSRC);
pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1)>> 4) ; pllm = ((RCC->PLLCKSELR & RCC_PLLCKSELR_DIVM1) >> 4);
pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN)>>RCC_PLLCFGR_PLL1FRACEN_Pos); pllfracen = ((RCC->PLLCFGR & RCC_PLLCFGR_PLL1FRACEN) >> RCC_PLLCFGR_PLL1FRACEN_Pos);
fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1)>> 3)); fracn1 = (float_t) (uint32_t) (pllfracen * ((RCC->PLL1FRACR & RCC_PLL1FRACR_FRACN1) >> 3));
if (pllm != 0U) if (pllm != 0U)
{ {
@@ -390,26 +399,34 @@ void SystemCoreClockUpdate (void)
{ {
case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */ case RCC_PLLCKSELR_PLLSRC_HSI: /* HSI used as PLL clock source */
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
pllvco = ( (float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); pllvco = ((float_t) hsivalue / (float_t) pllm) * (
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
fracn1 / (float_t) 0x2000) + (float_t) 1);
break; break;
case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */ case RCC_PLLCKSELR_PLLSRC_CSI: /* CSI used as PLL clock source */
pllvco = ((float_t)CSI_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); pllvco = ((float_t) CSI_VALUE / (float_t) pllm) * (
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
fracn1 / (float_t) 0x2000) + (float_t) 1);
break; break;
case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */ case RCC_PLLCKSELR_PLLSRC_HSE: /* HSE used as PLL clock source */
pllvco = ((float_t)HSE_VALUE / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); pllvco = ((float_t) HSE_VALUE / (float_t) pllm) * (
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
fracn1 / (float_t) 0x2000) + (float_t) 1);
break; break;
default: default:
hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)) ; hsivalue = (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
pllvco = ((float_t)hsivalue / (float_t)pllm) * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (fracn1/(float_t)0x2000) +(float_t)1 ); pllvco = ((float_t) hsivalue / (float_t) pllm) * (
(float_t) (uint32_t) (RCC->PLL1DIVR & RCC_PLL1DIVR_N1) + (
fracn1 / (float_t) 0x2000) + (float_t) 1);
break; break;
} }
pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >>9) + 1U ) ; pllp = (((RCC->PLL1DIVR & RCC_PLL1DIVR_P1) >> 9) + 1U);
common_system_clock = (uint32_t)(float_t)(pllvco/(float_t)pllp); common_system_clock = (uint32_t) (float_t) (pllvco / (float_t) pllp);
} }
else else
{ {
@@ -418,28 +435,30 @@ void SystemCoreClockUpdate (void)
break; break;
default: default:
common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV)>> 3)); common_system_clock = (uint32_t) (HSI_VALUE >> ((RCC->CR & RCC_CR_HSIDIV) >> 3));
break; break;
} }
/* Compute SystemClock frequency --------------------------------------------------*/ /* Compute SystemClock frequency --------------------------------------------------*/
#if defined (RCC_D1CFGR_D1CPRE) #if defined (RCC_D1CFGR_D1CPRE)
tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE)>> RCC_D1CFGR_D1CPRE_Pos]; tmp = D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */ /* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp; common_system_clock >>= tmp;
/* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */ /* SystemD2Clock frequency : CM4 CPU, AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE)>> RCC_D1CFGR_HPRE_Pos]) & 0x1FU)); SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->D1CFGR & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos])
& 0x1FU));
#else #else
tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE)>> RCC_CDCFGR1_CDCPRE_Pos]; tmp = D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos];
/* common_system_clock frequency : CM7 CPU frequency */ /* common_system_clock frequency : CM7 CPU frequency */
common_system_clock >>= tmp; common_system_clock >>= tmp;
/* SystemD2Clock frequency : AXI and AHBs Clock frequency */ /* SystemD2Clock frequency : AXI and AHBs Clock frequency */
SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE)>> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU)); SystemD2Clock = (common_system_clock >> ((D1CorePrescTable[
(RCC->CDCFGR1 & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU));
#endif #endif
@@ -476,68 +495,79 @@ void SystemCoreClockUpdate (void)
void ExitRun0Mode(void) void ExitRun0Mode(void)
{ {
#if defined(USE_PWR_LDO_SUPPLY) #if defined(USE_PWR_LDO_SUPPLY)
#if defined(SMPS) #if defined(SMPS)
/* Exit Run* mode by disabling SMPS and enabling LDO */ /* Exit Run* mode by disabling SMPS and enabling LDO */
PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN; PWR->CR3 = (PWR->CR3 & ~PWR_CR3_SMPSEN) | PWR_CR3_LDOEN;
#else #else
/* Enable LDO mode */ /* Enable LDO mode */
PWR->CR3 |= PWR_CR3_LDOEN; PWR->CR3 |= PWR_CR3_LDOEN;
#endif /* SMPS */ #endif /* SMPS */
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY) #elif defined(USE_PWR_EXTERNAL_SOURCE_SUPPLY)
#if defined(SMPS) #if defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_SMPSEN | PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
#else #else
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS; PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_BYPASS;
#endif /* SMPS */ #endif /* SMPS */
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS) #elif defined(USE_PWR_DIRECT_SMPS_SUPPLY) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 &= ~(PWR_CR3_LDOEN); PWR->CR3 &= ~(PWR_CR3_LDOEN);
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS) #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_LDO) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS) #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_LDO) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS) #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; PWR->CR3 |= PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS) #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN; PWR->CR3 |= PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS) #elif defined(USE_PWR_SMPS_1V8_SUPPLIES_EXT) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN |
PWR_CR3_BYPASS;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS) #elif defined(USE_PWR_SMPS_2V5_SUPPLIES_EXT) && defined(SMPS)
/* Exit Run* mode */ /* Exit Run* mode */
PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS; PWR->CR3 = (PWR->CR3 & ~(PWR_CR3_LDOEN)) | PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN |
PWR_CR3_BYPASS;
/* Wait till voltage level flag is set */ /* Wait till voltage level flag is set */
while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U) while ((PWR->CSR1 & PWR_CSR1_ACTVOSRDY) == 0U)
{} {
}
#else #else
/* No system power supply configuration is selected at exit Run* mode */ /* No system power supply configuration is selected at exit Run* mode */
#endif /* USE_PWR_LDO_SUPPLY */ #endif /* USE_PWR_LDO_SUPPLY */